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Observer arash-rezaee
Observer
6,655 Views
Registered: ‎02-01-2012

logicore FIR problem

hi every one. I am using FIR core to create low pass filter. I generated the coefficients from matlab(fdatool) and then put it into FIR core. my input has to be 16 bit and output has to be 16 bit too. the problem is, the output of the FIR core is square wave!!!!!!!!!!!!!!!!! Input signal is sine wave. what is the problem here? I also attached the coefficient file and the second page of setting for more information. my sampling rate is 95KHZ and the clock is 12.16MHz( sampling rate in fdatool is the same)  please some help me in this problem. Thankspage 2.jpg

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11 Replies
Xilinx Employee
Xilinx Employee
6,653 Views
Registered: ‎08-02-2011

Re: logicore FIR problem

Can you post a plot of your simulation showing this square wave? Please include the control signals as well.

 

What frequency is your input signal? Is it in the passband?

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Observer arash-rezaee
Observer
6,648 Views
Registered: ‎02-01-2012

Re: logicore FIR problem

I am working with DAC and see the output from Oscop. I don`t use simulation. my frequency is 5KHz and the sampling rate is 95KHz. filter works well and it will drop the signal above 16KHz but the output is square.
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Xilinx Employee
Xilinx Employee
6,645 Views
Registered: ‎08-02-2011

Re: logicore FIR problem

Well it could be any number of things, at that level. You should simulate first. At the very least, use chipscope to directly probe the core's signals.

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Observer arash-rezaee
Observer
6,637 Views
Registered: ‎02-01-2012

Re: logicore FIR problem

ok. here is the thing. I am beginner in xilinx and I don`t know how to simulate it. I am using 3s1600E FPGA. I use the xilinx core which provided for FIR filtering but it works like changing sine wave to square wave. if you want I can pass the CEO file to you and the picture of FIR filter setting. The output of my project is sine wave when I remove this FIR filter but it is square wave when I insert it. So please help me and guide me more to find out the problem. Thanks
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Xilinx Employee
Xilinx Employee
6,635 Views
Registered: ‎08-02-2011

Re: logicore FIR problem

Hello,

 

If you are a beginner, then it is especially important that you learn to simulate your designs properly. This will help provide verification that you are even using the core properly.

 

Have a look at this Application Note on writing testbenches:

http://www.xilinx.com/support/documentation/application_notes/xapp199.pdf

 

And also the ISE tutorial which describes step-by-step how to do a simulation:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ise_tutorial_ug695.pdf

 

You might also have a look at the ISIM tutorial:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/ug682.pdf

 

Or other tutorials for ISE Design Suite:

http://www.xilinx.com/support/documentation/dt_ise13-4_tutorials.htm

www.xilinx.com
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Observer arash-rezaee
Observer
6,632 Views
Registered: ‎02-01-2012

Re: logicore FIR problem

ok. But what can I do when my input data is from out side and I have to convert it to digital then process it? I mean my input data is voice which now I only use signal generator instead of voice signal. I will go through simulation BUTTTTTTTTTTTT remember that you didn`t answer my questionn ( at least you didn`t guide me a little) any way thanks
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Instructor
Instructor
6,629 Views
Registered: ‎08-14-2007

Re: logicore FIR problem

As noted, it's hard to guess the problem, but my instinct would say that if

the output is a square wave, then you have not carried enough bits through the

filter to handle the intermediate signal swing going through the filter.  You

could try reducing the input amplitude to see if the output waveform changes

shape.

 

-- Gabor

-- Gabor
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Observer arash-rezaee
Observer
6,626 Views
Registered: ‎02-01-2012

Re: logicore FIR problem

I changed the amplitude a lot and at all the time is square wave. when I generate VHDL file from fdatool it works very well and I have sine wave in output and filter works well but when I use this core it shows square wave!!!!!!!! I need to work with this core because later I want to put the coefficient I calculated form pre-emphasis filter. So I need to solve this problem. Thanks for reply
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Mentor hgleamon1
Mentor
6,616 Views
Registered: ‎11-14-2011

Re: logicore FIR problem

Hello,

 

I will admit immediately that I know very little about FIRs in Xilinx FPGAs (but this topic made for interesting reading anyway).

 

However, in your original message (posted on the Spartan 6 board), you state that your input and output data must be unsigned std_logic_vector and yet your screen-shot of the FIR core generation clearly shows both your coefficients and input data types to be signed.

 

Could this be affecting your data throughput?

 

Apologies if I'm completely off track.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Observer arash-rezaee
Observer
3,015 Views
Registered: ‎02-01-2012

Re: logicore FIR problem

acually I had mistake on that part. the input is signed and the output is also signed. both of them I need to be 16 bit and for this I change the output type to truncate LSB so I can change the output width to 16. it is really funny because it is about 2 days I am working on this topic and until now I got nothing.
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Xilinx Employee
Xilinx Employee
3,004 Views
Registered: ‎08-02-2011

Re: logicore FIR problem

No, you simply refuse to show data and won't learn how to use the core. No wonder it's not working how you'd expect...

 

Everyone here is happy to help and have provided many useful suggestions, but we can't debug something we know nothing about. You need to follow the suggestions given to you and if you still have a problem, come back when you can provide data for us to look at.

www.xilinx.com
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