02-08-2012 06:49 AM
hi every one. I am using FIR core to create low pass filter. I generated the coefficients from matlab(fdatool) and then put it into FIR core. my input has to be 16 bit and output has to be 16 bit too. the problem is, the output of the FIR core is square wave!!!!!!!!!!!!!!!!! Input signal is sine wave. what is the problem here? I also attached the coefficient file and the second page of setting for more information. my sampling rate is 95KHZ and the clock is 12.16MHz( sampling rate in fdatool is the same) please some help me in this problem. Thanks
02-08-2012 06:57 AM - edited 02-08-2012 06:58 AM
Can you post a plot of your simulation showing this square wave? Please include the control signals as well.
What frequency is your input signal? Is it in the passband?
02-08-2012 07:06 AM
02-08-2012 07:08 AM - edited 02-08-2012 07:08 AM
Well it could be any number of things, at that level. You should simulate first. At the very least, use chipscope to directly probe the core's signals.
02-08-2012 07:22 AM
02-08-2012 07:26 AM - edited 02-08-2012 07:27 AM
If you are a beginner, then it is especially important that you learn to simulate your designs properly. This will help provide verification that you are even using the core properly.
Have a look at this Application Note on writing testbenches:
And also the ISE tutorial which describes step-by-step how to do a simulation:
You might also have a look at the ISIM tutorial:
Or other tutorials for ISE Design Suite:
02-08-2012 07:33 AM
02-08-2012 07:45 AM
As noted, it's hard to guess the problem, but my instinct would say that if
the output is a square wave, then you have not carried enough bits through the
filter to handle the intermediate signal swing going through the filter. You
could try reducing the input amplitude to see if the output waveform changes
02-08-2012 07:52 AM
02-08-2012 01:11 PM
I will admit immediately that I know very little about FIRs in Xilinx FPGAs (but this topic made for interesting reading anyway).
However, in your original message (posted on the Spartan 6 board), you state that your input and output data must be unsigned std_logic_vector and yet your screen-shot of the FIR core generation clearly shows both your coefficients and input data types to be signed.
Could this be affecting your data throughput?
Apologies if I'm completely off track.
02-08-2012 10:37 PM
02-09-2012 06:09 AM
No, you simply refuse to show data and won't learn how to use the core. No wonder it's not working how you'd expect...
Everyone here is happy to help and have provided many useful suggestions, but we can't debug something we know nothing about. You need to follow the suggestions given to you and if you still have a problem, come back when you can provide data for us to look at.