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5,521 Views
Registered: ‎09-28-2011

vhdl generated files

Hi everybody,

 

here's my problem. I have to implement a signal processing algorithm on a FPGA. We've always used Sysgen.

the problem now is that we have to respect a coding standard, make a static analisys on the generated code and test on each module.

Sysgen generate a single big vhd file, but it would be much better to generate a single vhd file for each entity or package. Is there a way to automatically modify the single file in many vhd files, one foreach entity?

Moreover, is there a way to control how sysgen gives names to net or entities in the generated file?

 

we're developing a safety critical application and it's almost impossible to use a sysgen flow. The V&V would be too hard or even impossible.

 

 regards

 

Andrea

Andrea Campera
CEO and Founder
Campera, The DSP Company, www.camperadsp.com
Headquarter: Via Pellettier 57, 57122, Livorno (LI), Italy
Tel: +39-329-4677083, Fax: +39-0586-076557
email: a.campera@camperadsp.com
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7 Replies
Explorer
Explorer
5,519 Views
Registered: ‎08-14-2007

Re: vhdl generated files

If your sysgen design is hierarchical, you could potentially sysgen each block individually.  And then validate the HDL individually.  How are you planning to do that now?

 

If you have to validate at that level, it might be easier to write the HDL yourself...

 

What standard are you working to?  How safety critical is you application?

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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5,517 Views
Registered: ‎09-28-2011

Re: vhdl generated files

Martin,

 

i think it might be easier to write VHDL, at least the V&V process should be easier. we are planning to go that way, even if development time would be much longer

 

it's a railway application, IEC61508 (actually the equivalent italian standard), SIL4.

 

Validate each HDL individually could be cumbersome, sysgen put the conv_pkg and all entities toghether in a single file (actually it produces also individual vhd file for each IP used, for simulation purposes).

 

moreover, how can i use Xilinx IP's if on their header it's written

 

-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --

 

Andrea

Andrea Campera
CEO and Founder
Campera, The DSP Company, www.camperadsp.com
Headquarter: Via Pellettier 57, 57122, Livorno (LI), Italy
Tel: +39-329-4677083, Fax: +39-0586-076557
email: a.campera@camperadsp.com
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Explorer
Explorer
5,515 Views
Registered: ‎08-14-2007

Re: vhdl generated files

I think this bit is relevant:

"Customer assumes the sole risk"

:)

It says the same on the datasheets for the parts as well.

Designing a SIL4 system is a non-trivial task - using sysgen in the design process probably means a whole lot of extra validation work, yes.
Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
0 Kudos
5,513 Views
Registered: ‎09-28-2011

Re: vhdl generated files

We will assume that risk. That probably means we have to test IPs as black boxes.

 

that's a pity coz writing vhdl for signal processing (fixed or floating point) is not as easy as using Sysgen

 

BTW i don't understand why Sysgen produce such a big single HDL file. maybe for synthesizer optimization purposes?

 

there's no control at all on the generated files, not even on nets or entities names, i hope it will be included in future releases

 

Andrea

Andrea Campera
CEO and Founder
Campera, The DSP Company, www.camperadsp.com
Headquarter: Via Pellettier 57, 57122, Livorno (LI), Italy
Tel: +39-329-4677083, Fax: +39-0586-076557
email: a.campera@camperadsp.com
0 Kudos
Explorer
Explorer
5,511 Views
Registered: ‎08-14-2007

Re: vhdl generated files

It doesn't matter that it's all one big file - you can still write VHDL testbenches for each subblock that it generates, so if the entities are there, you can still "get at them" from the one big file. But that'll still be a bit of hassle and pain!

I don't think it's done that way for any purpose other than it's convenient to then deploy it to a higher-level tool by just bringing one self contained file in.
Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
0 Kudos
5,507 Views
Registered: ‎09-28-2011

Re: vhdl generated files

it matters if your coding standard says "one file for each entity" :) 

I guess many developers write one file for each entity, it's just a good rule if you have to write 100.000 lines of code

Andrea Campera
CEO and Founder
Campera, The DSP Company, www.camperadsp.com
Headquarter: Via Pellettier 57, 57122, Livorno (LI), Italy
Tel: +39-329-4677083, Fax: +39-0586-076557
email: a.campera@camperadsp.com
0 Kudos
Explorer
Explorer
5,500 Views
Registered: ‎08-14-2007

Re: vhdl generated files

Ahh.  Yes, I see your problem :)

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
0 Kudos