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Clock connection for AXI_VDMA IP

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Adventurer
Posts: 54
Registered: ‎09-21-2016
Accepted Solution

Clock connection for AXI_VDMA IP

Hi everyone,

 

I am confused about the clock connections of AXI_VDMA IP. The AXI_VDMA IP has 5 clocks. One is control clock (s_axi_lite_aclk ) , two clocks are memory map side clocks (m_axi_mm2s_aclk , m_axi_s2mm_aclk ) and another two clocks are streaming side clocks (s_axis_s2mm_aclk , m_axis_mm2s_aclk ) .

1.png

 

According to the user guide for AXI VDMA IP (v6.2, November 30,2016; page: 48), In synchronous mode, we will connect all these clocks to the same source.

But, in my case, the streaming side has different clocks, 80 MHZ and 108 MHZ (attached figure). According to the user guide (same page),    s_axi_lite_aclk < (m_axi_mm2s_aclk , m_axi_s2mm_aclk )

and                    (m_axi_mm2s_aclk , m_axi_s2mm_aclk ) >= (s_axis_s2mm_aclk , m_axis_mm2s_aclk

 

I need two different clocks in streaming side because my camera works at 80 MHZ and for the monitor (1280*1024,60 hz) I need 108 MHZ.

Although, my current configuration gives me the output from camera, but I am not sure my configuration is ok or not. That's why I want to discuss this matter.

 

Any suggestion will be really helpful.

 

Thank you

Rappy

 


Accepted Solutions
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Adventurer
Posts: 54
Registered: ‎09-21-2016

Re: Clock connection for AXI_VDMA IP

Hi @berker_atel,

 

Thank you for your reply. It was really helpful.

 

According to your suggestion, Xilinx Video in IP and Video Out IP has internal asynchronous FIFO. So, these IPs allow me to keep my stream clock independent from camera clock and monitor clock. For this, I need independent mode of operation for both IPs. Anyway, I am trying to apply this idea now. Hope it will work.

 

Thank you

Rappy Saha

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All Replies
Adventurer
Posts: 72
Registered: ‎11-09-2016

Re: Clock connection for AXI_VDMA IP

Hi,

Use to consider async FIFO for 80MHz & 108 MHz. Connect FIFO Slave side your camera data and Master side VDMA. It can works crossing clock domains manner. So you can connect all 5 clocks to 100MHz. 

 

This is not exact response, it might work.

Berker

Highlighted
Adventurer
Posts: 54
Registered: ‎09-21-2016

Re: Clock connection for AXI_VDMA IP

Hi @berker_atel,

 

Thank you for your reply. It was really helpful.

 

According to your suggestion, Xilinx Video in IP and Video Out IP has internal asynchronous FIFO. So, these IPs allow me to keep my stream clock independent from camera clock and monitor clock. For this, I need independent mode of operation for both IPs. Anyway, I am trying to apply this idea now. Hope it will work.

 

Thank you

Rappy Saha

Adventurer
Posts: 72
Registered: ‎11-09-2016

Re: Clock connection for AXI_VDMA IP

Hi,

A problem i have encountered before: My camera works 27MHz, but HP on Zynq works 100MHz. I use AXI4 Stream Data FIFO IP Core in Async clock mode. It generate Master Valid signal according to clocks(27,100) and DMA write data to DDR3 when AXIS valid is high. Or you can do your Fifo and pass --AXIS valid signal-- to DMA at proper time. You can simulate it in Vivado simulator.

 

Best Regards