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SDI Si5324 register values

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Participant
Posts: 40
Registered: ‎11-12-2008

SDI Si5324 register values

I'm doing a design on a 7K160 which has 2 SDI inputs and 2 outputs including 2 x Si5324 devices. In order to test the board I'd like to do a pass through of the SDIs similar to that in XAPP592. The Si5324s will be programmed via IIC from a Microblaze. Is there a simple listing of the required Si5324 register values please?

 

There doesn't seem to be one in the XAPP592 example code and the .coe file for this is in an unexplained format - impossible to decipher. Preferably a simple C header format of Address, Reg_value would be ideal.

 

My design will exclusively be HD-SDI i.e. 148.5MHz if that makes any difference.

 

Thanks,

Rog.

Observer
Posts: 20
Registered: ‎07-18-2011

Re: SDI Si5324 register values

If you know what frequencies you need, you can go to the Silicon Labs software download page and download the DSPLLsim software.   It supports the Si5324, and has an option to generate an output register map file based on your clock inputs and outputs (Options->Save Register Map File...)

 

https://www.silabs.com/documents/public/software/PrecisionClock_EVBSoftware.zip

 

https://www.silabs.com/products/development-tools/software/clock

 

 

Example output file for a 100MHz input clock and 148.5MHz output clock:

 

#HEADER
# Date: Tuesday, October 10, 2017 11:40 AM
# File Version: 3
# Software Name: Precision Clock EVB Software
# Software Version: 5.1
# Software Date: July 23, 2014
# Part number: Si5324
#END_HEADER
#PROFILE
# Name: Si5324
#INPUT
# Name: CKIN
# Channel: 1
# Frequency (MHz): 100.000000
# N3: 100
# Maximum (MHz): 106.060606
# Minimum (MHz): 90.722035
#END_INPUT
#PLL
# Name: PLL
# Frequency (MHz): 5346.000000
# f3 (MHz): 1.000000
# N1_HS: 6
# N2_HS: 11
# N2_LS: 486
# Phase Offset Resolution (ns): 1.12233
# BWSEL_REG Option: Frequency (Hz)
#  9:    8
#  8:   16
#  7:   32
#  6:   65
#  5:  132
#  4:  268
#  3:  556
#END_PLL
#OUTPUT
# Name: CKOUT
# Channel: 1
# Frequency (MHz): 148.500000
# NC1_LS: 6
# CKOUT1 to CKIN1 Ratio: 297 / 200
# Maximum (MHz): 157.499999
# Minimum (MHz): 134.722221
#END_OUTPUT
#CONTROL_FIELD
# Register-based Controls
#        FREE_RUN_EN: 0x0
#    CKOUT_ALWAYS_ON: 0x0
#         BYPASS_REG: 0x0
#          CK_PRIOR2: 0x1
#          CK_PRIOR1: 0x0
#          CKSEL_REG: 0x0
#              DHOLD: 0x0
#            SQ_ICAL: 0x1
#          BWSEL_REG: 0x9
#        AUTOSEL_REG: 0x2
#           HIST_DEL: 0x12
#              ICMOS: 0x3
#              SLEEP: 0x0
#         SFOUT2_REG: 0x5
#         SFOUT1_REG: 0x5
#          FOSREFSEL: 0x2
#             HLOG_2: 0x0
#             HLOG_1: 0x0
#           HIST_AVG: 0x18
#          DSBL2_REG: 0x1
#          DSBL1_REG: 0x0
#             PD_CK2: 0x1
#             PD_CK1: 0x0
#         FLAT_VALID: 0x1
#             FOS_EN: 0x0
#            FOS_THR: 0x1
#            VALTIME: 0x1
#              LOCKT: 0x1
#        CK2_BAD_PIN: 0x1
#        CK1_BAD_PIN: 0x1
#            LOL_PIN: 0x1
#            INT_PIN: 0x0
#         INCDEC_PIN: 0x1
#       CK1_ACTV_PIN: 0x1
#          CKSEL_PIN: 0x1
#        CK_ACTV_POL: 0x1
#         CK_BAD_POL: 0x1
#            LOL_POL: 0x1
#            INT_POL: 0x1
#           LOS2_MSK: 0x1
#           LOS1_MSK: 0x1
#           LOSX_MSK: 0x1
#           FOS2_MSK: 0x1
#           FOS1_MSK: 0x1
#            LOL_MSK: 0x1
#              N1_HS: 0x2
#             NC1_LS: 0x5
#             NC2_LS: 0x5
#              N2_LS: 0x1E5
#              N2_HS: 0x7
#                N31: 0x63
#                N32: 0x63
#         CLKIN2RATE: 0x0
#         CLKIN1RATE: 0x0
#           FASTLOCK: 0x1
#            LOS1_EN: 0x3
#            LOS2_EN: 0x3
#            FOS1_EN: 0x1
#            FOS2_EN: 0x1
#   INDEPENDENTSKEW1: 0x0
#   INDEPENDENTSKEW2: 0x0
#END_CONTROL_FIELD
#REGISTER_MAP
  0, 14h
  1, E4h
  2, 92h
  3, 15h
  4, 92h
  5, EDh
  6, 2Dh
  7, 2Ah
  8, 00h
  9, C0h
 10, 08h
 11, 42h
 19, 29h
 20, 3Eh
 21, FFh
 22, DFh
 23, 1Fh
 24, 3Fh
 25, 40h
 31, 00h
 32, 00h
 33, 05h
 34, 00h
 35, 00h
 36, 05h
 40, E0h
 41, 01h
 42, E5h
 43, 00h
 44, 00h
 45, 63h
 46, 00h
 47, 00h
 48, 63h
 55, 00h
131, 1Fh
132, 02h
137, 01h
138, 0Fh
139, FFh
142, 00h
143, 00h
136, 40h
#END_REGISTER_MAP
#END_PROFILE

Participant
Posts: 40
Registered: ‎11-12-2008

Re: SDI Si5324 register values

Thanks a lot for this.

It's just to be used to reduce jitter from a recovered clock so I presume the input and output are both 148.5MHz. There's an example for the KC705 / SDI daughterboard and it was this that I was ideally looking for.

 

Rog.

Observer
Posts: 20
Registered: ‎07-18-2011

Re: SDI Si5324 register values

I've used the Si5327d as an HD/3G-SDI video clock cleaner/multiplier for exactly that application.  The Si5327d is essentially the same part as the Si5324d, not quite as good jitter specs, 0.5pS vs 0.29pS, but less expensive.   The resulting SDI output jitter performance is quite good, well within the 3G-SDI specs.

 

I used their app to generate the register values for each desired output frequency, stored them in a small onboard distributed ROM, and programmed it with a SPI routine in the FPGA.

Participant
Posts: 40
Registered: ‎11-12-2008

Re: SDI Si5324 register values

Thanks, so is the idea to set the output frequency exactly the same as the input and maybe modify the PLL BW as required?

 

Rog.

Observer
Posts: 20
Registered: ‎07-18-2011

Re: SDI Si5324 register values

It depends on your application, but yes, if you have the same frequency clock coming in as you need going out, then just set your PLL output frequency to match the input.  You can change it on-the-fly through the SPi interface.

 

As for the bandwidth, you will want to set the PLL bandwidth to the 8Hz setting (I believe that is the lowest, and default value in the DSPLLsim app) in order to meet the jitter specs of HD/3G-SDI, which requires a max 10Hz bandwidth.   Silicon labs has a good paper on the subject in their AN377 app note, see section 5.1 Jitter Filtering, and Section 5. Jitter Requirements for Video Clocks, which illustrate the required bandwidth:

 

https://www.silabs.com/documents/public/application-notes/AN377.pdf

 

Also, you will need to use a small clock-crossing FIFO to transfer your video data from the noisy clock domain to the clean clock domain.    Since they are at the same frequency long-term, you shouldn't need a very big FIFO, just enough to handle the short-term jitter on the input.   I used the 16 deep, independent clock, distributed-RAM FIFO IP for the task.

 

 

 

 

Participant
Posts: 40
Registered: ‎11-12-2008

Re: SDI Si5324 register values

Thanks very much for your help. I'll look at that AN.

 

Thanks again,

Rog.