06-19-2017 02:49 PM
I am running a behavioral simulation of an SDI RX using the guidelines and files from XAPP1097 (v1.0.1) using Vivado 2016.4. I'm using dru_sim.v for the simulation and supplying a 50 MHz free running clock for the SDI and DRP clock (FXDCLK_FREQ = 50000000 and DRPCLK_PERIOD = 20) and supplying a 148.5 MHz ref clk. I've run the simulation for 10ms and rx_fabric_reset_out = 1 and rx_mode_locked = 0. When I look at the a7gtp_sdi_wrapper_gtrxreset_seq module I see the state machine stuck at state wait_pmareset waiting for a falling edge on RXPMARESETDONE. Module inputs RXPMARESETDONE stays high and GTRXRESET_IN stays low. The sequence of events are as follows:
1. RXPMARESETDONE goes low to high at 180 NS.
2. GTRXRESET_IN goes low to high at 540 NS.
3. RXPMARESETDONE goes low at 621 NS.
4. DRPRDY has two positive pulses.
5. GTRXRESET_IN goes low at 1760 NS.
6. RXPMARESETDONE has a 20 PS positive glitch at 2020 NS (may not be consequential. This does not generate an input to the state machine).
7. RXPMARESETDONE goes high at 2180 NS. The state machine is stuck at state wait_pmareset waiting for a falling edge of RXPMARESETDONE which never occurs.
8. Inputs remain static to the a7gtp_sdi_wrapper_gtrxreset_seq.v module and its output DRP_OP_DONE stays low which appears to prevent initialization from proceeding.
Any help would be appreciated. Thanks in advance.
06-20-2017 01:21 AM
Are you using the version 1.01 of the xapp1097? Refer to AR#60303
Hope that helps,
06-20-2017 11:53 AM
Yes. I'm also using dru_sim.v. I'll try simulating the ac701_sdi_demo provided in XAPP1097 and see if I get a different result.