10-11-2017 08:57 AM
I am pretty new at FPGA design so I am sorry if I'm asking a rather silly question. I've been playing around in Vivado and I wanted to incorporate the Xilinx Viterbi Decoder IP core into my ZedBoard basic design. But I'm not quite sure how. Should I create a port directly that would be input and output of the decoder? If that is so, I have no use of the other cores in the base design? And I am confused about DSTAT input and output interface, how to connect it. Thank you in advance for help!
11-24-2017 02:12 AM
12-04-2017 02:00 AM
thank you for your help. I've tried packaging my own IP and Vivado didn't offer me to run block automation when I added it in my new block design. I've also tried it with Xilinx Viterbi evaluation IP core and still nothing. The problem is I don't know what IPs I need to add to my block design to make it work. I have this only, shown in picture.
Kind regards and thank you once again,