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Viterbi Decoder IP connection

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Visitor
Posts: 4
Registered: ‎07-18-2016

Viterbi Decoder IP connection

Hi everyone,

 

I am pretty new at FPGA design so I am sorry if I'm asking a rather silly question. I've been playing around in Vivado and I wanted to incorporate the Xilinx Viterbi Decoder IP core into my ZedBoard basic design. But I'm not quite sure how. Should I create a port directly that would be input and output of the decoder? If that is so, I have no use of the other cores in the base design? And I am confused about DSTAT input and output interface, how to connect it. Thank you in advance for help!

Moderator
Posts: 5,501
Registered: ‎08-01-2008

Re: Viterbi Decoder IP connection

You required to create custom IP interface for Viterbi decoder for Zedboard .

Here is steps which you can follow and implement with Viterbi core
https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-creating-custom-ip-cores/start
Thanks and Regards
Balkrishan
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Visitor
Posts: 4
Registered: ‎07-18-2016

Re: Viterbi Decoder IP connection

Hi,

 

thank you for your help. I've tried packaging my own IP and Vivado didn't offer me to run block automation when I added it in my new block design. I've also tried it with Xilinx Viterbi evaluation IP core and still nothing. The problem is I don't know what IPs I need to add to my block design to make it work. I have this only, shown in picture.

 

Kind regards and thank you once again,

Nives

viterbi_dec.png