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melang
Contributor
Contributor
13,023 Views
Registered: ‎09-29-2013

Hardware Manager error(relative ila ip core)(vivado 13.4)

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hello.

 

im using vivado 13.4. when i finsihed  implementation, i tried to check my design using ila ip core(3.0-Rev.1).

 

when i open hardware manager i`ve got a problem.

 

there was a solution that the device probes file is up-to-date. then, re-program the device.

 

so, i checked Hardware Device Properties > probes file :  /impl_1/debug_nets.ltx

 

i think it is ok. it is my design.

 

and than i check the error massage.

 

[Labtools 27-1974] Mismatch between the design programmed into the device xc7vx690t_0 and the probes file D:/HDL/Ethernet_1G/1000BASE_X/1000BASE_X.runs/impl_1/debug_nets.ltx.

The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).

 

the device design has not any core. but i added ila ip core in my design. 

 

could somebody help me?

 

error.jpg
1 Solution

Accepted Solutions
venkata
Moderator
Moderator
16,892 Views
Registered: ‎02-16-2010
By free running clock, it means the clock input from an on board oscillator.

Please check the clock connected to the debug cores is not available for some reason. This is the most probable reason.
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17 Replies
vemulad
Xilinx Employee
Xilinx Employee
13,017 Views
Registered: ‎09-20-2012
Hi,

I have seen some cases where this error goes off if you create a new project. Try creating new project and check if that helps.

Ensure that the ILA clock is free running clock.

Thanks,
Deepika.
Thanks,
Deepika.
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venkata
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Registered: ‎02-16-2010
This following are possible causes/solutions of this error:

1. ​Cases were found that creating a new project resolves the error.
2. Make sure the .bit file and the .ltx file assigned to this device match each other.
3. Make sure the capture clock to the ILA is a free running clock
4. Make sure that timing requirement has been met after inserting Debug cores.
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melang
Contributor
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Registered: ‎09-29-2013

hello, 

i have tried to do it. 

1. Cases were found that creating a new project resolves the error. 

- > it have still made a error.

2. Make sure the .bit file and the .ltx file assigned to this device match each other.

->i have already did it. - > it have still made a error.

3. Make sure the capture clock to the ILA is a free running clock.

-> i don`t understand. what is the free running clock?

-> i have designed clk_wizard(v5.1). inclk = 200MHz(input pin) , debug output clk = 200MHz .

-> debug output clk is the input clock in ILA core.

 

----------------------

 

anyway, when i open synthesizerd design, number of dbg_hub cell pins were 55. but,  my debug design are 71 cell pins.

 

i think dbg_hub and ila core are related.

but i can`t modify properties of dbg_hub. 

 

help me plz.

 

 

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venkata
Moderator
Moderator
16,893 Views
Registered: ‎02-16-2010
By free running clock, it means the clock input from an on board oscillator.

Please check the clock connected to the debug cores is not available for some reason. This is the most probable reason.
------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

yxcvbn1
Explorer
Explorer
12,847 Views
Registered: ‎12-29-2007

Hi, not sure why this topic is marked as 'solved' ... anyway,

I have the same issue on my side. I checked the 4 points mentioned above, did all the work to implement my sources into an new,  fresh project. It did not help at all.

I also checked that the ILA core is correct synthesized and implemented. It is.

 

Any suggestion what to do next?

 

#############################################

INFO: [Labtools 27-1432] Device xc7k325t (JTAG device index = 0) is programmed with a design that has 1 ILA core(s) in it.
ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7k325t (JTAG device index = 0) and the probes file C:/_XILINX/PROJECTS/CMV2000onFMC_1/CMV2000onFMC_1.runs/impl_1/debug_nets.ltx.
 The device core at location user chain=1 index=0, has 0 ILA Input port(s), but the core in the probes file has 1 ILA Input port(s).
Resolution: Make sure the device probes file is up-to-date, then re-program the device.

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venkata
Moderator
Moderator
12,820 Views
Registered: ‎02-16-2010
For this error,
1. Check if the debug_nets.ltx. is the correct probes file generated along with the latest bit file
2. If not, you can point to the latest probes file and refresh the device
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yxcvbn1
Explorer
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12,814 Views
Registered: ‎12-29-2007

Hi,

thank you for offering help!

I checked this point and it is setup correctly:

- in 'Hardware Device Properties' both files, the *.bit and the *.ltx are correctly addressed.

- the LTX has the right number of probes in its structure

- the schematic after Synthesis show the expected dbg_hub and ILA core setup and connection

- I can see the ILA probe nets in implemented design device view.

 

I have created another small project and I can reproduce the issue here as well.

##########################

 Mismatch between the design programmed into the device xc7k325t (JTAG device index = 0) and the probes file C:/_XILINX/PROJECTS/CMV2000onFMC_2/CMV2000onFMC_2.runs/impl_1/debug_nets.ltx.
 The device core at location user chain=1 index=0, has 0 ILA Input port(s), but the core in the probes file has 1 ILA Input port(s).
Resolution: Make sure the device probes file is up-to-date, then re-program the device.

##########################

 

From what I see here I think the problem is inverese: the LTX (and schematic/implementation) is correct (1 ILA) but the BIT file is corrupt (0 ILA). To check the bit file I deleted both LTX and BIT file and re-run synthesis/implementation. I checked twice that both files are new created and used in HW manager.

Unfortunately the result is worse as before.

 

I have attached the LTX file, not sure if you can see something here.

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yxcvbn1
Explorer
Explorer
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Registered: ‎12-29-2007

short update, I checked the 'report_debug_core' command which proves the assumtion from above:

 

report_debug_core
Known Debug Core Specs:
 labtools_ila_v3
 labtools_xsdbmasterlib_v2
 chipscope_ila_v1
 labtools_ilalib_v2
 labtools_ila_v2
 chipscope_icon_v1
 agilent_atc2_v1
 chipscope_vio_v1
 labtools_xsdbslavelib_v2
 labtools_vio_v2
 labtools_vio_v3
Known Debug Cores:
 dbg_hub (labtools_xsdbmasterlib_v2) [blackbox]
 params:
  C_USER_SCAN_CHAIN 1
  C_XSDB_NUM_SLAVES 1
  component_name dbg_hub_CV
 ila_0 (labtools_ila_v3) [implemented]
 params:
  ALL_PROBE_SAME_MU true
  ALL_PROBE_SAME_MU_CNT 1
  C_ADV_TRIGGER false
  C_DATA_DEPTH 1024
  C_EN_STRG_QUAL false
  C_INPUT_PIPE_STAGES 0
  C_NUM_OF_PROBES 1
  C_PROBE0_WIDTH 30
  C_TRIGIN_EN 0
  C_TRIGOUT_EN 0
  component_name design_2_ila_0_0

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rholschbach
Visitor
Visitor
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Registered: ‎11-18-2013

I see this with VIVADO 2014 has anyone found a solution.

 

ERROR: [Labtools 27-1973] Mismatch between the design programmed into the device xc7z020 (JTAG device index = 1) and the probes file C:/VIVADO_2014_zed/zed_brd_fmc_usb_rog/zed_brd_fmc_usb_rog.runs/impl_1/debug_nets.ltx.
 The device core at location user chain=1 index=0, has 1 ILA Input port(s), but the core in the probes file has 14 ILA Input port(s).
Resolution: Make sure the device probes file is up-to-date, then re-program the device.

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yxcvbn1
Explorer
Explorer
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Registered: ‎12-29-2007

After I was informed that ILA clock must be higher than JTAG clock I did not run into this issue again. In 2014.1 there may be a warning for a wrong clock ratio. Not sure about this.

What is your ILA clock compared to JTAG clock?

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rholschbach
Visitor
Visitor
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Registered: ‎11-18-2013

Yes my JTAG clock was faster than the ILA clock.   Slowed down the JTAG some and that took care of this.

 

Thanks,

 

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andrewgd
Visitor
Visitor
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Registered: ‎12-05-2013

 

I have seen this problem in 2014.2, but not at first.

 

Up until yesterday, I have had no problem with the ILA in 2014.2 when the ILA library core is connected in a Zynq system block diagram. Also in this system block diagram is a custom Packaged IP core which provides outputs (including the clock) to the ILA block. No problems debuggin these signals!

 

So, my next change was to remove the ILA block from the system top level and instantiate the ILA block in the top level of my custom IP project, then re-package the IP. I then imported the IP into my system project (literally deleted the old IP block, then added the new IP). The ILA block is now in the system hierachy under my custom IP block.

 

I then generated a bit file with no problems. Next opened up the hardware manager > open new target , etc. and now I get the following error:

 

  • [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file C:/SVN_dsp_fpga/zsdr/system/system.runs/impl_1/debug_nets.ltx. The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s). Resolution: Make sure the device probes file is up-to-date, then re-program the device.

On further investigation:

 

Synthesis Log:

INFO: [Synth 8-256] done synthesizing module 'ila_v4_0_ila_core' (428#1) [c:/SVN_dsp_fpga/zsdr/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/ila_v4_0/hdl/verilog/ila_v4_0_ila_core.v:77]
INFO: [Synth 8-256] done synthesizing module 'ila_v4_0_ila__parameterized0' (429#1) [c:/SVN_dsp_fpga/zsdr/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/ila_v4_0/hdl/verilog/ila_v4_0_ila.v:79]
INFO: [Synth 8-256] done synthesizing module 'ila_0' (430#1) [c:/SVN_dsp_fpga/zsdr/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/synth/ila_0.vhd:65]

Implementation log shows the following warnings (repeated several times) :

Parsing XDC File [c:/***/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/constraints/ila.xdc] for cell 'system_i/sdr_rx_0/U0/i_ila_0'
WARNING: [Vivado 12-180] No cells matched '*'. [c:/***/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/constraints/ila.xdc:4]
WARNING: [Vivado 12-180] No cells matched '*'. [c:/***/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/constraints/ila.xdc:4]
CRITICAL WARNING: [Vivado 12-1387] No valid object(s) found for set_false_path constraint with option '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer*/din_reg_reg*" && (PRIMITIVE_TYPE =~ FLOP_LATCH.*.* || PRIMITIVE_TYPE =~ RTL_REGISTER.flop.* || PRIMITIVE_TYPE =~ REGISTER.SDR.*) }]'. [c:/***/system/system.srcs/sources_1/bd/system/ip/system_sdr_rx_0_1/sdr_rx.srcs/sources_1/ip/ila_0/constraints/ila.xdc:4]

I have Reset Output Products, and re-run. Same problem. The only change to my design was to place the ILA in the Packaged IP block rather than the system block diagram.

 

The device probes file also seems to have been generated correctly? The question is, does the ILA component have to be at the system top level for the Hardware Manager to actually detect it? What other files can I look at to check the ILA is actually in the design or to force Vivado to see this core if it is there?

 

Kind Regards,

Andy

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andrewgd
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Registered: ‎12-05-2013

To add to the post above , I have now removed the ILA from the IP block and attempted to "Set Up Debug" directly in the System project.

 

I still get the same problem:

 

ERROR: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z020_1 and the probes file C:/SVN_dsp_fpga/zsdr/system/system.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file has 1 ILA core(s) and 0 VIO core(s).

Resolution: Make sure the device probes file is up-to-date, then re-program the device.

 

Please can anyone provide any explanation/fix?

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pulim
Xilinx Employee
Xilinx Employee
7,062 Views
Registered: ‎02-16-2014

Hi,

 

This following are possible fixes for this error:

    • Ensure that the .bit file and the .ltx file assigned to this device match each other.

 

    • Ensure that the capture clock to the ILA is a free running clock

 

    • Ensure that timing requirement has been met after inserting Debug cores.

 

    • The error can be caused by a Signal Integrity issue on the board. 
      A case was found where the issue was caused by a bad USB Cable.

 

  • In one case creating a new project resolved the error.

It's always good practice to start a new thread when you are posting your query.

If you are replying to an old thread it may not be recognized by the people.

 

 

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andrewgd
Visitor
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Registered: ‎12-05-2013

Hi,

 

In response to your reply, aa I stated earlier, I have previously had this working with the ILA in the top level block diagram connected up to exactly the same signals, same clock, no timing errors, same hardware/cable, same files, etc. so the first 4 points are not a solution.

 

In terms of asking a customer to spend a lot of time creating a new project - has this been investigated by Xilinx and is Is this actually a solution? Can Xilinx re-create this problem?

 

Do you want me to start this in a new thread? Will it make some difference for you?

 

Kind Regards,

Andy

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rforsyth
Observer
Observer
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Registered: ‎03-25-2013

I resolved this by moving my ILA to a faster clock. I was using 4.8 MHz which was apparently too slow. I was using the slowest JTAG clock available.

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236646495
Newbie
Newbie
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Registered: ‎03-20-2015

I find a strange apprance.

when i use sdk to debug and open hardware manage,it work well and there are signals in debug probes,but when i program device in the hardware manage,tcl will show the mismatch.The .bit and .ltx are same. 

Althougth i don't konw why,i solved this problem by using the clock generated by the pll and changing a slower JTAG clock.

 

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