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7,999 Views
Registered: ‎07-24-2014

10 Gb Eth MAC Byte Ordering on AXI tdata lanes

Looking at document   pg072-ten-gig-eth-mac_v13_1  on page 43, Figure 3-9, what is the ordering of the tdata bytes in to the proper bits on the ethernet link?

 

Specifically, Does 48-bit Destination Address (DA) bits 47:0 go on lines tdata 47:0, or does ethernet link DA[47:40) go on lane tdata 7:0, and so on.

 

Another way to answer my question:  For the Source Address, in Fig 3-9, on the first 64-bit word transfer, on tdata[55:48], is that the most or least significant byte of the Source Address 48-bit address?

 

Thank you for time

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Xilinx Employee
Xilinx Employee
7,980 Views
Registered: ‎02-06-2013

Re: 10 Gb Eth MAC Byte Ordering on AXI tdata lanes

HI

 

The destination address must be supplied with the first byte in lane 0 and the first byte is the lower byte in address.

 

Followed by the source address following the same address mapping.

Regards,

Satish

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Xilinx Employee
Xilinx Employee
7,976 Views
Registered: ‎02-06-2013

Re: 10 Gb Eth MAC Byte Ordering on AXI tdata lanes

Hi

 

You can also simulate the example design provided with the core and look into the test bench frames propagation through the core to have more clear understanding.

Regards,

Satish

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7,935 Views
Registered: ‎07-24-2014

Re: 10 Gb Eth MAC Byte Ordering on AXI tdata lanes

Thanks for the feedback. I'll have to simulate to be sure. The MAC DA and SA and L/T look like they are little endian (so DA byte on tdata(47:40) would be the first byte out on the ethernet wire, with tdata(47) the first bit.

 

Thanks for your input.

 

Regards,

Steve

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