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Adventurer
Adventurer
447 Views
Registered: ‎04-25-2017

1G/10G/25G switching Ethernet subsystem gives error while IP product generation

I am trying to implement a design with base microblaze design with 1G/10G/25G switching Ethernet subsystem IP. While doing that Vivado 2018.3 design gives error while generating the output products. The errors are also strange.

[Synth 8-5809] Error generated from encrypted envelope. ["<project>/project.srcs/sources_1/bd/project/ipshared/5446/hdl/xxv_ethernet_v2_5_vl_rfs.v":17042]

[Synth 8-448] named port connection 'ctl_rx_test_pattern_0' does not exist for instance 'project_ethernet_1_10_25g_0_0_pcs' of module 'project_ethernet_1_10_25g_0_0_xxv_eth_pcs' ["project/Tproject.srcs/sources_1/bd/project/ip/project_ethernet_1_10_25g_0_0/ethernet_1_10_25g_v2_2_0/project_ethernet_1_10_25g_0_0_top.v":475]

[Synth 8-6156] failed synthesizing module 'TargetBoard_BIST_ethernet_1_10_25g_0_0_xxv_eth_mac_top' ["<project>/project.srcs/sources_1/bd/project/ip/project/ip_4/xxv_ethernet_v2_5_0/project_ethernet_1_10_25g_0_0_xxv_eth_mac_top.v":53]

25G_etherrnet_switching_ip.png
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Xilinx Employee
Xilinx Employee
294 Views
Registered: ‎05-14-2008

Re: 1G/10G/25G switching Ethernet subsystem gives error while IP product generation

Please provide the .xci file of the 1G/10G/25G switching Ethernet subsystem IP that you're using.

And what is the device part that you're using?

-vivian

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