05-21-2015 01:14 PM
We just upgrade the vivado tool from 2014.2 to 2014.4.
I found out that when I right click on an IP and chose"Edit in IP Packager", there are some warning message:
WARNING: [IP_Flow 19-3833] Not packaging sources file marked as disabled: '*.edf'. (I changed the path to be *)
Each edf file will have one warning message.
And in "File Groups" the edf files are no longer in "Verilog Synthesis" group. (Previously in 2014.2 they were there.)
I tried manually add edf file into the group, another critical warning pop out:
[IP_Flow 19-3355] File group 'xilinx_verilogsynthesis' contains both HDL and structural netlist files. The flow may not compile any of the HDL file. The user should consider moving the structural netlist file to the top of the file group.
How do I add edf files to "the top of the file group"?
How to add edf files in IP packager?
05-22-2015 02:12 AM - edited 05-22-2015 02:15 AM
Is the EDIF file shown under top module in hierarchy window?
If you open IP packager project and run Implementation does it complete successfully. Is the EDIF file picked properly during Implementation?
I have created a simple test case in Vivado 2014.4 and it is working fine. Attaching it here.
05-22-2015 10:36 AM
I looked at your project.
The difference is that we even have an edf file for the top module.
So in the Hierarchy, we only have one .v file which is the top module, and we have the edf file for top module, and some other edf files for the down level modules.
I added the edf files to the project so that they are in the Design Source, but all the edf files are in the same level with top.v(maybe not the name "top").
And in the File Group of Package IP, I didn't see the edf files.
I run Implementation, it said "[Place 30-494] The design is empty" meaning it didn't pick the edf files.
But the same setting works fine with vivado 2014.2.
I then re-packaged IP in "Package IP" and close the project, and re-open the project by "Edit in IP packager" the edf files doesn't show under "Design Sources" in the "Hierarchy".
05-25-2015 07:41 AM
Does the EDIF file name match with the module name which you have specified in instantiation in top level file?
Can you attach a snapshot showing the hierarchy window?
05-26-2015 04:55 PM
This Ip works fine with vivado 2014.2, so the name for edf files should match with the .v file, as I didn't modify the source files.
05-26-2015 05:05 PM
I also modified your sample project, I removed the top.v file and set up_counter.v as top. (Which is more like our setting)
As you can see the edf file is not in the "File Groups" list, and implementation as design is empty.
05-26-2015 10:06 PM
From your snapshot,
why do you have both netlist and HDL of module up_counter added to the design? Which one do you want the tool to use?
05-27-2015 11:49 AM
The .v file only defines the input/output of the module, and .edf file contains the logic.
I think that's the way we do that, am I wrong?
05-27-2015 09:22 PM - edited 05-27-2015 09:24 PM
If you want to package the EDIF file as top module then remove this verilog file which is wrapper of EDIF file.
You can add this verilog wrapper file when adding the user IP in your top level design.
When you have both wrapper and EDIF file then the IP packager packages only one file which is set as top module.
Another method is to instantiate this EDIF file in a top module as I have done in my test design(attached in my earlier post).
05-28-2015 10:58 AM
I tried to remove .v file from project and set .edf as top, and I can't run impl as "no netlist available" and can't run synth as "no HDL source in file set"
You said "When you have both wrapper and EDIF file then the IP packager packages only one file which is set as top module." Is it only for 2014.4? Because we did the samething in 2014.2 and never got this problem.