2017.2 - [PSU-1] critical warning with basic Zynq design on DDR interface

[ronnywebers]

Currently migrating from 2015.4 to 2017.2

To test my Vivado 2017.2 installation, I create a very simple block Zynq design :

* create new project using Zedboard

* create bd

* add Zynq IP to the bd

* connect FCLK_CLK0 to M_AXI_GP0_ACLK (if left unconnected, this throws an error when validating the bd)

* hit 'validate'

this results in 2 critical warnings regarding DDR :

CRITICAL WARNING: [PSU-1]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 has negative value -0.009 . PS DDR interfaces might fail when entering negative DQS skew values. 
CRITICAL WARNING: [PSU-2]  Parameter : PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 has negative value -0.061 . PS DDR interfaces might fail when entering negative DQS skew values. 

can someone clarify these critical warnings? I think I've never seen this in 2015.4, and I don't like any critical warning in a design :-) Is this something related to the Zedboard config file that is not up-to-date with the 2017.2 version?

[florentw · Accepted solution]

Hi @ronnywebers,

This is coming from the board definition file for the Zedboard (I have the same warning with a project from scratch) and the configuration form the zedboard.

I wouldn't worry to much as it is the same parameter as in previous versions (and the board was working). Only a critical warning has been added to make customer designing the own board be careful.

EDIT: I confirm that this critical warning has been added because customers entering negative DQS skew values in the GUI had a failed DDR interface. However, negative DQS skew values are technically supported by ZDDR. So it is still ok to have them on the zedboard. This warning might be considered for new board design

Regards,

Florent