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Observer rbarris
Observer
1,669 Views
Registered: ‎06-08-2015

2017.3 adding "_0" suffix to external port names in block design

I have a relatively simple Zynq design using a single RTL module with one AXI-Slave port and a handful of ports which get marked external so they can be matched up with device pins using the constraint file.

 

Before 2017.3, the port name at the top level port list of the RTL module would be mirrored to the external signal node after selecting each port in the block design editor and right-clicking to "Make External".  So a port named "com3_rx" would show an external signal node called by the same name after being made external.

Under 2017.3 this behavior has changed, when I select a port on the RTL module and make it external, the name of the external node now has a "_0" suffix, so I would see something like "com3_rx_0" instead of "com3_rx".  Unfortunately my automation which generates the XDC files to hook up the device pins, still thinks the signal will be named "com3_rx" and things go south after that.

On a hunch I added another instance of my RTL module and sure enough any port made external on that instance was instead given a "_1" suffix instead of "_0".  So it's tied to presence of multiple instances of a module in a design ?  Is there a way to tell the system "I only have one module" and get those extra suffixes elided ?  If I select 40 port pins and make them all external in one operation, I'd like to avoid renaming them one by one.

OK, so this looks like a new feature / behavior which unfortunately causes some conflicts in my automation scripts where the old alignment of port name and external node name is assumed.

So what I want to ask is, where is this newer behavior documented, and/or are there any tips on how to control or alter this behavior in the IDE ?  Plainly I can make changes to my scripts to try and follow the new behavior, but I'd like to understand more explicitly where it gets the choice of "_0" / "_1" etc.

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4 Replies
Observer rbarris
Observer
1,665 Views
Registered: ‎06-08-2015

Re: 2017.3 adding "_0" suffix to external port names in block design

It seems like it's worse than I thought, if I go through this flow, starting with a mostly empty design:

a) insert three instances of my module without making any pins external

b) selecting one pin on the third module (which has been named by the block design editor "module_2", following "module_0" / "module_1"

c) making that port external...

--> It suffixes that signal name with "_0" and not "_2".

This is not great.
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Observer rbarris
Observer
1,579 Views
Registered: ‎06-08-2015

Re: 2017.3 adding "_0" suffix to external port names in block design

(bump) Can a Vivado expert explain this change in behavior ?

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Adventurer
Adventurer
1,197 Views
Registered: ‎06-13-2017

Re: 2017.3 adding "_0" suffix to external port names in block design

Probably you've already solved the problem, but this is a solution that I just found:

1. run reset_project from TCL

2. open *.bd and *.bxml and replace all "_0" with "" (no character).

3. Rebuild

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Xilinx Employee
Xilinx Employee
1,184 Views
Registered: ‎07-22-2008

Re: 2017.3 adding "_0" suffix to external port names in block design

Please do not shoot the messenger but it seems this is a matter of preference.

I did a quick check and found that this was changed due a customer request (CR# 971877).  The request was to make the auto naming more consistent by adding the _0 to the first instance of an auto added port.

 

The appended value string has nothing to do with the name of the IP instance or the order the instance was added to the BD.  This has not changed.  The only change was the addition of the "_0" for the first auto added port for a pin of a given name.

 

If you want to trim the port names back to the way they were before you could run the following two commands

 

foreach my_port [get_bd_ports *_0] {[set_property name [string range $my_port 1 [string last _ $my_port]-1] [get_bd_ports $my_port]]}

foreach my_port [get_bd_intf_ports *_0] {[set_property name [string range $my_port 1 [string last _ $my_port]-1] [get_bd_intf_ports $my_port]]}

 

I also checked to see if there was a hidden option or preference to revert to the Vivado 2017.2 behavior.  There is not.

 

 

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