04-06-2018 12:08 PM - edited 04-06-2018 12:09 PM
A 3rd party IP vendor has delivered an eval version of his IP core in the form of a .dcp file.
(He has also delivered a VHDL package file containing the component declaration).
I would like to instantiate this IP into IP Integrator as an IP block. Is there an preferred way to achieve this?
Another complication - the vendor has stated that the .dcp was generated using 2016.3 tools. I need to use 2017.4. Does this affect this flow?
04-06-2018 06:36 PM
This is something that is being looked at for future releases but currently (Vivado 2018.1 and earlier) niether module reference or packaging a user IP allows the use of a dcp submodule. In order to use this customer IP you would have to create a top level RTL and instantiate both the BD and the 3rd party IP and create BD ports specifically for connecting to the IP outside the BD.
04-09-2018 11:46 AM
OK so I think I found out how to do this.
I added the component declaration and the .dcp file to a new Vivado 2016.4 Post Synthesis project.
I then opened the synthesized design and did write_vhdl <component name>.
In my 2017.4 project, I then used the Module Reference flow to add the core to my top level .bd.
04-12-2018 04:16 AM
Thanks a lot for letting us know and we are glad to see that you have found out a valid workaround to this issue.
As your issue is solved, please mark your response as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions), so the topic can be completed then. We appreciate your help.
Thanks in advance and have a great day.