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406860
Explorer
Explorer
11,819 Views
Registered: ‎12-02-2013

3rd party IP integration in Vivado

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I have a board from vendor that includes their IP to handle I/O and some other

functionality.  The way we add our IP is by taking their design which includes

a black-box place holder and adding the ngc from a different project that our

IP has been developed in.

 

As we move to Vivado I would like to have 1 project where it is our vendor's

top level design, but instead of an ,ngc for our IP, I have the verilog source.

 

My first attempt at building his project resulted in errror related to the read-only

attribute of the black-box our vendor instantiated as a placeholder in the top level

design.

 

At this point I have three questions:

 

1. Is it even possible to have such a development environment in Vivado?  One

    that has ngc at the top level with verilog source for IP that is pullled into the

    top level design?

 

2. Are there any issues (other than getting the read-only attribute changed) that I

    need to be aware of to create a functional projec/development environment.

 

3. Will Vivado know what to do with the ngcs when I synthesize the design to

    to synthesize the verilog source that has been added?

 

Thanks,

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vemulad
Xilinx Employee
Xilinx Employee
19,659 Views
Registered: ‎09-20-2012
Hi,

From your details it looks like you want to have ngc as top with verilog files as sub modules.

It is not possible to have this in single project. You can try below.

Synthesize the verilog files in out of context mode in a different project and add the post synthesis dcp to your main project. In this way your main project contains all netlists and implementation can be run.

Thanks,
Deepika.
Thanks,
Deepika.
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406860
Explorer
Explorer
11,766 Views
Registered: ‎12-02-2013

I tried rebuilding the project as a source based project with my verilog as the top level.  I then

added the 3rd party ngc and constraint file to the project. 

 

I was able to synthesize the design, but it looks like the 3rd party ngc and possibly the

constraint file did not get picked up or used.  I/O utilization is at 110%, slice lut utilization

is about 1/2 what I was expecting and the synthesized design only shows my IP.

 

When I try to specifiy our vendor's ngc as the top level, I get an error almost immediately

that says no verilog source could be found.

 

Any thoughts on what I'm doing wrong?

 

Thanks,

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vemulad
Xilinx Employee
Xilinx Employee
11,755 Views
Registered: ‎09-20-2012

Hi,

 

Can you run Implementation and see if that passes?

 

If the tool is not able to pick the NGC files for submodules it fails at opt_design phase. If the Implementation passes, open the implemented design and see if you can see the IP submodule logic in it.

 

If you want to have NGC as top then you need to create a post synthesis project as shown below.

 

Capture.PNG

 

Thanks,

Deepika.

Thanks,
Deepika.
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406860
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Explorer
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Registered: ‎12-02-2013

Deepika,

 

I created an RTL based project so that I could get the synthesis part of the flow.

I am able to run Implementation and it passes however it doesn't appear to pick

up the rest of the design.  I get many critical warnings related to objects not being found.

Here are a few:

 

[Common 17-55] 'set_property' expects at least one object. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":3]

 

Line#3 of the xdc: set_property PACKAGE_PIN K28 [get_ports clk50fpga]

 

[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_ports clk50fpga]'. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":6]

 

Line#6 of the xdc: create_clock -period 20.000 -name cc_clk50fpga [get_ports clk50fpga]

 

[Vivado 12-1387] No valid object(s) found for set_clock_groups constraint with option '-group [get_clocks cc_clk50fpga]'. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":13]

 

Line#13 of the xdc: set_clock_groups -name async_clk50fpga_cpu_clk -asynchronous -group [get_clocks cc_clk50fpga] -group [get_clocks cc_cpu_clk] 

 

[Vivado 12-1387] No valid object(s) found for create_clock constraint with option '-objects [get_pins ten_gig_eth_pcs_pma_v2_6_example_design_2/ibufds_instQ1_CLK0/O]'. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":89]

 

Line#89 of the xdc: create_clock -name ten_gig_eth_pcs_pma_v2_6_refclk -period 6.400 [get_pins ten_gig_eth_pcs_pma_v2_6_example_design_2/ibufds_instQ1_CLK0/O]

 

[Common 17-55] 'set_property' expects at least one object. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":208]

 

Line#208 of the xdc: set_property IOSTANDARD LVCMOS33 [get_ports bcm_rstn]

 

[Vivado 12-1433] Expecting a non-empty list of cells to be added to the pblock.  Please verify the correctness of the <cells> argument. ["/home/creed/working/hw/vivado2.4/vivado2.4/vivado2.4.srcs/constrs_1/imports/vivado2.4/fpga_7k325t_cip05Nov14.xdc":1246]

 

Line#1246 of the xdc: add_cells_to_pblock pblock_pcs_pma0 [get_cells -quiet [list ten_gig_eth_pcs_pma_v2_6_example_design_2/example_design0/ten_gig_eth_pcs_pma_block/ten_gig_eth_pcs_pma_core]]

All of these reference parts of the design that are in the ngc we receive from our vendor. 

 

As an FYI  The post-implementation utilization remained low.  The device view shows a routed design,

but only shows my ip.  

 

In my Synthesis view of my sources, I do see that the ngc that contains the rest of the design is under

a folder called Unreferenced.  Is there a way to get it pulled in/

 

Thanks for your help. 

 

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vemulad
Xilinx Employee
Xilinx Employee
11,682 Views
Registered: ‎09-20-2012

Hi,

 

Can you show the snapshot of sources window?

 

What is the current top module of the design? Is it RTL or NGC?

 

Thanks,

Deepika.

Thanks,
Deepika.
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406860
Explorer
Explorer
11,619 Views
Registered: ‎12-02-2013

Deepika,

 

Attached is a screen grab of my sources window.  The project is an RTL project.

with the customer_ip_example.v as the top level.

 

In reality fpga_7k325t_cip.ngc is the top level.  It used to pull in customer_ip_example.ngc

which was synthesized in a seperate project.  I would like to have a single project that

contains the toplevel fpga_7k325t_cip.ngc as the top level (the .xdc matches that .ngc)

and pull in the verilog source for customer_ip_example.v and all of the verilog modules

underneath it.

 

Thanks,

Vivado2-4SourceFiles18Nov14.jpg
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vemulad
Xilinx Employee
Xilinx Employee
19,660 Views
Registered: ‎09-20-2012
Hi,

From your details it looks like you want to have ngc as top with verilog files as sub modules.

It is not possible to have this in single project. You can try below.

Synthesize the verilog files in out of context mode in a different project and add the post synthesis dcp to your main project. In this way your main project contains all netlists and implementation can be run.

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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406860
Explorer
Explorer
11,599 Views
Registered: ‎12-02-2013

Deepika,

 

Thanks for your help.  I have conitnued to work on this with an Avnet FAE.  It seems like

he was able to do this in a simple project.  I am attempting to re-produce his results in

my project.  He created a RTL project where the top level was an ngc.  The ngc pulled in

a vhdl file of a 2-input AND gate.  He said the key was to make the vhdl the top level and

then right-click on the .ngc, scroll down to "Used In" and UNCHECK "Synthesis" on the

ngc.  He said he was able to synthesize the vhdl, and when he went through Implementation,

Vivado picked up his .ngc.

 

I haven't been succesful yet, but I am hoping that I've missed something in his instructions.

If I am able to get it to work, I'll update this thread with the necessary steps and mark that as

the solution.

 

Any chance Xilinx can make this enhancement in a future release?  It would be convenient to

be able to work with a single project when the project includes thrid party IP.

 

Do you know if the "Used In" property was meant to be used in this manner?

 

Thanks again for your help.

 

Regards,

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