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Mentor
Mentor
330 Views
Registered: ‎06-09-2011

A question mark in front of ports of created IP

Hi all,

I have created a custom IP from an RTL that it has AXI stream S/M as well as clock & reset. I have followed naming conventions of AXI interface that enables Vivado to infer AXI stream for those S/M AXIS. I have also tried to define some parameters like FREQ_HZ for all these ports. I can not understand why Vivado places question marks in front of AXI bus of my IP and even those reset and clocks. Did I miss anything during IP creation? How can I fix this issue? Some of those question marks are shown in the below picture

QuestionMark.jpg

I would appreciate any help.

 

Thanks,
Hossein
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4 Replies
Teacher
Teacher
268 Views
Registered: ‎01-28-2008

Hi @embedded 

  While I haven't seen such question mark in custom IP, here's a few things to try.

- Does validation of block design change anything? Any warning messages?

- Renaming the aclk/aresetn ports to have the "axi[s]" in them, i.e. axis_aclk.

- Adding the attributes "X_INTERFACE_INFO*" to these ports:

  ATTRIBUTE X_INTERFACE_INFO      : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;

  ATTRIBUTE X_INTERFACE_INFO of s_axi_aclk : SIGNAL is "xilinx.com:signal:clock:1.0 s_axi_aclk CLK";
  ATTRIBUTE X_INTERFACE_PARAMETER of s_axi_aclk : SIGNAL is "ASSOCIATED_BUSIF s_axi, ASSOCIATED_RESET s_axi_aresetn FREQ_HZ 100000000";

  ATTRIBUTE X_INTERFACE_INFO of s_axi_aresetn : SIGNAL is "xilinx.com:signal:reset:1.0 s_axi_aresetn RST";
  ATTRIBUTE X_INTERFACE_PARAMETER of s_axi_aresetn : SIGNAL is "POLARITY ACTIVE_LOW";

Thanks,

-Pat

 

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Mentor
Mentor
223 Views
Registered: ‎06-09-2011

Hi @patocarr ,

Thank you for your answer. I have similar issue with SI/MI ports which is not shown in this picture. I compared my created core - simple VHDL - with what Vivado creates and noticed that it has some tcl file for bd. but, I couldn't see it in my custom created IP - that has a VHDL only.

Ip with bdEdited.png

 

 Could it be possible that all those question marks show up in canvas because there is no BD file in my custom IP?

 

Thanks,
Hossein
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Teacher
Teacher
209 Views
Registered: ‎01-28-2008

Hi @embedded 

  I believe the bd.tcl would be added by the packager if you had a block design in the module to be packaged. I've checked my own IP and it doesn't have it either. Do you see this bd.tcl when you subsequently edit the packaged IP?

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

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Mentor
Mentor
183 Views
Registered: ‎06-09-2011

Hi @patocarr ,

If I package my VHDL I do not see such file. As I said, it is part of the IPs you create using "Create New AXI Peripheral"

Thanks,
Hossein
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