I am currently working on interfacing of ADS5294( 8 channel serial ADC) with ZC706 FPGA board through FMC card. I am using ADC in 1 wire, 2's complement , MSB first mode.These configurations i can do in GUI of Ads5294 and according to that written a code in vhdl.The code basically converts differential ended output to single ended output as it is serial ADC. For current situation, I am sampling ADC at 20 MHZ, hence i will get Frame clock as 20 MHz , bit clock as 140 MHz and output data rate is 280 MHz ( as per the timing diagram attached to this post). The rest of the diagram (DDS, FIR, MULTIPLIER, DMA) is working on 20 MHz clock which is generated by clocking wizard.
1. Can i use this frame clock (output from ads5294 vhdl code) to clock all the ip's in the design?
2. I have tried this but while implementing this design , iam getting errors.
If the design would clock by frame clock, this would be very useful for me as it solves my problem. I am trying to build whole design with one clock as it avoids use of FIFO generator( clock domain changing) .