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Contributor
Contributor
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Registered: ‎01-09-2018

ASYNC_REG

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I have a cdc circuit that contains a pair of FF's.

This module is old and rather dated.  ISE era.

I have a few questions in regards to bringing this cdc up to date.

The flops have ASYNC_REG, RLOC, SHREG_EXTRACT attached to net between the FF's and the Q of the last FF.

 

Here are the questions:

1.)  If using ASYNC_REG, is RLOC required.  Seems to be redundant.

2.)  Is SHREG_EXTRACT required or does the ASYNC_REG constraint force a real standalone FF.

3.)  How does ASYNC_REG constraint propagated?  Upstream FF's or Downstream FF's?  I could not find anywhere in Xilinx documentation information regarding how these constraints propagate when attached to nets.  I thought it was upstream, but now I'm not sure.

 

Thanks,
Michael 

 

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Guide
Guide
1,032 Views
Registered: ‎01-23-2009

Let's be careful here - there are two things to consider:

 

a) the path between the last FF on the source clock domain and the first flip-flop on the destination domain

b) the paths (potentially several) between the Q and the D of the synchronization flip-flops on the destination domain (assuming a simple synchronizer).

 

The b) case is easy - all that is required is the ASYNC_REG property to be set on all the flip-flops in the metastability reduction chain (all the back to back FFs on the destination domain). Nothing else is required; the ASYNC_REG constrains placement (so no RLOC required) and makes the FFs behave as if they have DONT_TOUCH on it (so the tool cannot infer SRLs for these, hence no SHREG_EXTRACT is required).

 

The rules for the ASYNC_REG is very simple. If two flip-flops that are connected from Q->D both have the ASYNC_REG property on them, then the two flip-flops are considered part of the same metastability chain - there is no propagation rules, both flip-flops need the property. If the chain consists of 3 FFs, then all 3 need the ASYNC_REG property. This property can only be attached to flip-flops (which are cells) - they have no meaning if/when attached to nets or pins.

 

The a) case is more complex - it depends entirely on how the synchronizer works. If the synchronizer is synchronizing a slow changing 1 bit signal (i.e. not a bus, and no more than 1 transition every 3+ destination clocks) then the path between them is either false (if you don't care about latency) or should be constrained by a set_max_delay -datapath_only if you want to limit the latency of the clock crossing (one usually uses a the period of the faster of the two clocks to limit latency). If the clock domain crossing circuit (CDCC) is more complex (crossing a bus or an "event") then a different CDCC is required, and it may need different constraints on the paths between domains.

 

Avrum

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Highlighted
Guide
Guide
1,033 Views
Registered: ‎01-23-2009

Let's be careful here - there are two things to consider:

 

a) the path between the last FF on the source clock domain and the first flip-flop on the destination domain

b) the paths (potentially several) between the Q and the D of the synchronization flip-flops on the destination domain (assuming a simple synchronizer).

 

The b) case is easy - all that is required is the ASYNC_REG property to be set on all the flip-flops in the metastability reduction chain (all the back to back FFs on the destination domain). Nothing else is required; the ASYNC_REG constrains placement (so no RLOC required) and makes the FFs behave as if they have DONT_TOUCH on it (so the tool cannot infer SRLs for these, hence no SHREG_EXTRACT is required).

 

The rules for the ASYNC_REG is very simple. If two flip-flops that are connected from Q->D both have the ASYNC_REG property on them, then the two flip-flops are considered part of the same metastability chain - there is no propagation rules, both flip-flops need the property. If the chain consists of 3 FFs, then all 3 need the ASYNC_REG property. This property can only be attached to flip-flops (which are cells) - they have no meaning if/when attached to nets or pins.

 

The a) case is more complex - it depends entirely on how the synchronizer works. If the synchronizer is synchronizing a slow changing 1 bit signal (i.e. not a bus, and no more than 1 transition every 3+ destination clocks) then the path between them is either false (if you don't care about latency) or should be constrained by a set_max_delay -datapath_only if you want to limit the latency of the clock crossing (one usually uses a the period of the faster of the two clocks to limit latency). If the clock domain crossing circuit (CDCC) is more complex (crossing a bus or an "event") then a different CDCC is required, and it may need different constraints on the paths between domains.

 

Avrum

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Teacher
Teacher
1,024 Views
Registered: ‎07-09-2009

what chip are you looking at ?

 

there are new macros that cover CDC for some chips,

 

for example, page 5 here

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_1/ug974-vivado-ultrascale-libraries.pdf

 

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