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Explorer
Explorer
6,115 Views
Registered: ‎07-14-2014

AXI Crossbar Master Address setting

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Hi,

 

I am in the process of putting together some IP that include a number of other IP blocks (3x(Aurora + AXIS FIFO + I2C + UART) ) that all have AXI interfaces. In the top level of the IP I don't really want to expose all of the AXI interfaces to the top level (as there are over 6 of them so far) and would prefer to put an AXI crossbar in the IP and connect the output from that to all of the slaves. This means that I therefore only have to expose a single AXI interface to the outside world, making the connection much simpler (essentially making it like a DisplayPort or HDMI subsystem)

 

When instantiating the crossbar I have to specify the Base address of each of the AXI masters but I will not know this information until the IP is instantiated into the final design.

 

How do I configure the crossbar so that I can pass a top level Base addr into the IP block (as a VHDL generic) and then have the base addresses of the AXI master interface set as offsets from the specified base addr (similar to the DisplayPort Subsystem)

 

I can't seem to see an obvious way of doing this as the IP seems to hard code everything at generation time. If it was just using generics it would be simple but I can't seem to see how to do this using IP (unless I'm being either blind or stupid, either is equally possible). There is obviously a way of doing it as the subsystems manage it.

 

I am hoping it is not some awkward TCL trick as I'm trying to keep this in the VHDL domain as far as possible. (NOTE: I'm not doing this in IP Integrator if it makes any difference)

 

Any suggestions would be appreciated.

 

Regards

 

Simon

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Scholar markcurry
Scholar
10,888 Views
Registered: ‎09-16-2009

Re: AXI Crossbar Master Address setting

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Simon,

 

(Sorry for the delayed response - I'm not getting notifications for some reason...)

 

It's as simple as you think. Just find the RTL in the tree, and instantiate it. 

 

Finding the RTL can be trouble - we usually use the whatever GUI tool of the day Xilinx is forcing on us, and create a default configuration.  Make sure you deselect OOC flows ( another dumb idea, IMHO ).  Within the output of the tool, it'll generate the RTL files, and a top-level example design or wrapper.  We use the example design as reference for our own parameterized version of the Xilinx core.  All the other lower level RTL the tool generates gets checked into revision control.

 

All other junk files produced are thrown away.  We never use the GUI again.

 

The whiz-bang GUI tool didn't allow you to set the number of Master ports - even though the underlying IP supported up to 16 masters, and 16 slaves, just fine.  And it's even documented in DS768 (although that document refers to the 1.06 core - I've found it sufficient to use as reference for the 1.7 version).  There was another thread somewhere asking about the datasheet for the 1.7 version of the core.  As far as I know, that got no response ( but I've not checked the thread nor the tools in a while).

 

Good luck.

 

--Mark

 

 

7 Replies
Scholar markcurry
Scholar
6,084 Views
Registered: ‎09-16-2009

Re: AXI Crossbar Master Address setting

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Simon,

 

You say you're not using IP integrator (good choice!), but I'm wondering how you're instantiating the axi_interconnect?

 

We're using the axi_interconnect v1_7 - I believe the last useful version Xilinx released which included the RTL code and had nice flexible top level interface controlled by parameters.

 

In that version the addressing was simply controlled by the C_M_AXI_BASE_ADDR, and C_M_AXI_HIGH_ADDR parameters (generics).

 

Just set those appropriately, and you're done.  We're doing this right now, and it works great.

 

I'm guessing that this is NOT the version of the axi_interconnect you're using, and as such this solution won't work for you.  So, perhaps you can fill in some more on how you're getting your crossbar?  (I'm actually curious - as we're stuck at version v1_7)

 

Regards,

 

Mark

 

 

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Teacher muzaffer
Teacher
6,075 Views
Registered: ‎03-31-2012

Re: AXI Crossbar Master Address setting

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@markcurry I am not sure why you think 1.7 is the latest RTL for the crossbar. The version in 2015.4 is 2.1 and it has the following (among others) generics in it and it seems like the RTL is also available (in 

/opt/Xilinx/Vivado/2015.4/data/ip/xilinx/axi_crossbar_v2_1/hdl/verilog):

 

   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b1}},

   parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_HIGH_ADDR = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}},

 

So you should be able to use this version too. 

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Explorer
Explorer
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Registered: ‎07-14-2014

Re: AXI Crossbar Master Address setting

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Mark,

 

I suspect this is where I am going wrong. I am currently adding the IP from the IP catalog and instantiating that through the RTL. I wasn't aware that I could instantiate it directly without generating the IP first.

 

When I looked at adding the axi_interconnect_v1_7 as IP there didn't seem to be a way of setting the number of master interfaces from the GUI so I guess I overlooked that and went straight to generating the crossbar instead.

 

Are there any special tricks to instantiating the axi_interconnect directly (without generating the IP) or is it just a case of finding the module name in C:\Xilinx\Vivado\2016.1\data\ip\xilinx and then instantiate as normal (setting the appropriate generics)?

 

Apologies if that's a dumb question, my brain seems to be stuck in "Everything must be IP" which Xilinx seem to be pushing, but it seems much less flexible at build time. (i.e. I can't just change a couple of top level generic parameters and have it ripple through the entire design (or at least I haven't found a simple of doing this yet)).

 

Regards

 

Simon

 

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Scholar markcurry
Scholar
10,889 Views
Registered: ‎09-16-2009

Re: AXI Crossbar Master Address setting

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Simon,

 

(Sorry for the delayed response - I'm not getting notifications for some reason...)

 

It's as simple as you think. Just find the RTL in the tree, and instantiate it. 

 

Finding the RTL can be trouble - we usually use the whatever GUI tool of the day Xilinx is forcing on us, and create a default configuration.  Make sure you deselect OOC flows ( another dumb idea, IMHO ).  Within the output of the tool, it'll generate the RTL files, and a top-level example design or wrapper.  We use the example design as reference for our own parameterized version of the Xilinx core.  All the other lower level RTL the tool generates gets checked into revision control.

 

All other junk files produced are thrown away.  We never use the GUI again.

 

The whiz-bang GUI tool didn't allow you to set the number of Master ports - even though the underlying IP supported up to 16 masters, and 16 slaves, just fine.  And it's even documented in DS768 (although that document refers to the 1.06 core - I've found it sufficient to use as reference for the 1.7 version).  There was another thread somewhere asking about the datasheet for the 1.7 version of the core.  As far as I know, that got no response ( but I've not checked the thread nor the tools in a while).

 

Good luck.

 

--Mark

 

 

Scholar markcurry
Scholar
5,969 Views
Registered: ‎09-16-2009

Re: AXI Crossbar Master Address setting

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Muzaffer,

 

Thanks for the pointer.  I'll have to look close at that version of the "axi_crossbar" (2.1).

 

Looking again, I see the "axi_interconnect" v1.7, that we're using - with parameterized RTL available.

I see, "axi_interconnect" v2.1, which DOES NOT have RTL available.  Seeing this I probably stopped looking figuring Xilinx was leaving us with a GUI only path forward (which we'll never use).

 

But, as you've shown there's the "axi_crossbar" v2.1 RTL available.  Hmm, need to dig deeper.  Maybe Xilinx has not left us totally left on our own moving forward.  Wonder how Xilinx categories what's a "axi_interconnect" and what's a "axi_crossbar", and how they're different.  The same version numbers leave me wondering...

 

Regards,

 

Mark

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Scholar markcurry
Scholar
5,967 Views
Registered: ‎09-16-2009

Re: AXI Crossbar Master Address setting

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Ok, I've taken a quick look.  The axi_crossbar does NOT contain per-port parameters for the ACLK* parameters and DATA_WIDTH parameters.  The axi_interconnect does (There's probably other parameters I missing in my quick look)

 

So, one assumes the axi_crossbar is a sub-module of the full axi_interconnect.  The crossbar is the kernel of the processing, but it operates only only fully synchronous ports, and ports of all the same DATA_WIDTH.

 

One assumes that the GUI tool now selectively instantiates clock-crossing, and data-conversion (probably protocol too) bridges to make all ports the same type, and then instantiates the fully synchronous RTL axi_crossbar.  It appears Xilinx no longer creates an RTL version of the axi_interconnect - just the axi_crossbar. 

 

We'll probably continue using 1.7 axi_interconnect for now - as we do utilize those features.  (and it's been working fine for years).  But, if starting from scratch, I'd consider the 2.1 crossbar today.  I'd rather Xilinx created the RTL as they did before.  Do it once, instead of N customers each doing it. But it's not too much trouble to add it yourself.

 

Regards,

 

Mark

 

 

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Explorer
Explorer
5,944 Views
Registered: ‎07-14-2014

Re: AXI Crossbar Master Address setting

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Mark,

 

Apologies for my delayed response to your delayed response, I don't seem to be getting notifications to things on the forum unless I subscribe to them. Odd. Anyway....

 

I'll give it a go when I get back on the project. Many thanks for your input on this, it has been a great help.

 

It's also nice to see that someone else dislikes the IPI as much as I do. I was starting to think I was the only one! It's just a pity Xilinx seem to be forcing everyone down that route

 

Many thanks

 

Simon

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