10-12-2016 03:40 PM
I am trying to transfer the data from the FIFO IP to DDR. If I want to write the data to different DDR addresses, I could use the DMA IP with the multiple channel support (set 2 MM2S channels).
However, I saw a lot of posts for the configuration of the multiple channel support on the forum, which are completed by the software. Could I configure these setting in the hardware level (e.g., add some VHDL code)?
Also, there is a post (https://forums.xilinx.com/t5/Design-Entry/difference-between-AXI-Datamover-and-AXI-DMA/td-p/657268) mentioned that using DataMover is more customized. So should I use the DataMover in this case?
10-12-2016 06:53 PM
10-13-2016 11:05 AM
I am trying to transfer the data from the FIFO IP to DDR. If I want to write the data to different
DDR addresses, I could use the DMA IP with the multiple channel support
As you've described it, I don't see why you would need to use multi channel.
You have control over the granularity of a packet and the src/dest addresses at the packet level. There's no reason why you couldn't use the DMA with one channel and set the transfer length=FIFO depth (or whatever) and dst_addr=addr_a. When that completes, initiate a new transfer to dst_addr=addr_b. You could also use scatter gather for more sophisticated control (though that would be a lot more complex to manage if you want to just do hardware control instead of software).
If this is indeed your use case, my opinion is that the AXI DMA will be easier to use. To set this up, you only need to write 3 registers via AXI Lite which is a very simple FSM to write in hardware. The datamover command interface is a little more troublesome to deal with for most folks (in my experience).
10-14-2016 10:11 AM
For writing 3 registers via AXI LIte, did you mean that I need to customize a AXI Lite IP, which performs two transfers?
Also, you mentioned the packet level, and could you please give me more details about it? How can I control it in the hardware side, because I think the packet level is supposed in the software side. Please correct me, if I am wrong, since I am pretty new for the block design.
10-14-2016 10:29 AM - edited 10-14-2016 10:32 AM
>> For writing 3 registers via AXI LIte, did you mean that I need to customize a AXI Lite IP, which performs two transfers?
No you have to code an axi-lite master which is a relatively simple state machine to do the writes periodically as you need new transfers.
As to packet processing, it is not only for software. At the hardware level, you need to get a certain amount of data popped from the FIFO, write it to a target address in DDR. The software has to allocate the memory and give you the memory but the hardware should decide how much to read from the fifo and/or report how much data there was to read to software side too. This size needs to be programmed into the dma controller and also be returned to software.
10-14-2016 02:15 PM - edited 10-14-2016 02:18 PM
I agree with @muzaffer comments. Just to add another perspective to it...
The way I think about it is that the hardware actually dictates the packet size and the software responds appropriately. At the DMA hardware level, tlast signal ultimately determines the end of a packet. On the software side, you'd better have set up the DMA with enough space to handle the max possible size that a packet can be. In register direct mode (i.e. no scatter gather), it's as simple as length_register >= tlast_period (in bytes).
In register direct mode, the software kicks off one transfer, waits for it to complete (i.e. tlast), and then the DMA goes idle until it gets another command.
So if you want to control this in hardware, you would first have some mechanism for generating tlast at appropriate intervals. Then in your AXI Lite master state machine, you would do something like:
1) Write Control register: to enable interrupt on complete
2) Write to Destination Address register: Where you want the data to go
3) Write to the Length register: How big is the packet (at least as big as tlast period in bytes)
4) Wait for interrupt
5) Optional - Read status register: Check for errors and handle them somehow
6) Go back to 1 to set up the next transfer
10-23-2016 12:33 PM
Thank you so much for your replies! The idea is pretty decent and totally makes sense for me.
However, when I looked deep into the source code, I got stuck on the following problems:
1. AXI-lite master interface in the PS (namely M_AXI_GP0), looks transparent for the function blocks, and I didn't found state machine inside of the source code.
2. I also checked the AXI-lite slave interface in the DMA IP. However, there is no state machine and it is transparent, which is similar to the AXI-lite master interface in the PS.
3. But I found the S2MM state machine code in the DMA IP, which includes state transmission only. If I understand your replies correctly, I am supposed to revise both state transmission and registers in the same source code file. Otherwise, I also need to track and revise the source address and destination address in other files. In the entire DMA source code, the register module, control module and transmit module are written separately, which looks pretty complicated to modify.
3. To make the entire process work, I need to write a function block in the hardware that can control the data transfer of DMA. So this function module should be able to write the destination address, data source address and the length to the DMA registers, right? BTW, the another point confusing me is the "descriptor" mentioned in the Xilinx DMA manual. Does it stand for the source address or destination address?
4. Besides, the final data transfer work is done by AXI DataMover IP, which is inside of the DMA IP, so I am thinking that if I can modify this IP to finish this work.
10-27-2016 01:54 PM