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181 Views
Registered: ‎04-28-2015

AXI Direct Memory Access(7.1) IP transfer length issue.

I have instantiated the AXI Direct Memory Access(7.1) IP core in my Zynq design. However I can't seem to use the maximum transfer length indicated in the documentation. The IP core does not allow me to configure the transfer length to more than 23 bits. The S2MM_LENGTH (S2MM DMA Buffer Length Register – Offset 58h) register indicates 26 bits?

I am using Vivado 2016.3

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166 Views
Registered: ‎03-17-2019

Re: AXI Direct Memory Access(7.1) IP transfer length issue.

hello,

if you want to set the length of S2MM , you should write to the register offset 0x58 and not in the IP GUI. in the IP GUI keep it 23 bit for buffering.

 

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162 Views
Registered: ‎04-28-2015

Re: AXI Direct Memory Access(7.1) IP transfer length issue.

Thanks for the reply. The S/W guy is telling me that he would have to change the Xilinx provided S/W driver to do what you suggest. The driver baulks if he tries to use bits higher than 23.

The Vivado IP block does not allow me go higher than 23.

I am not sure what you mean by buffering in this case?

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144 Views
Registered: ‎06-05-2018

Re: AXI Direct Memory Access(7.1) IP transfer length issue.

You are working as standalone or linux OS? Could you please share you design block and the configuration of the dma gui? 

 

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136 Views
Registered: ‎04-28-2015

Re: AXI Direct Memory Access(7.1) IP transfer length issue.

I am not sure how to share a design block. The design is very large. I have attached snapshots however of the things you asked.

The code in our CPU 1(which is control of the DMA) is bare metal code. It uses the Xilinx driver for the DMA block. It transfers data to memory. CPU 0 has Linux. It takes and uses the data that CPU0 stored into memory.

DMA_Config.JPG
DMA_Block.JPG
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