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Registered: ‎11-03-2020

AXI Ethernet Lite Core behaviour to AXI master bus

Dear All,


I've generated a AXI Master which I use in combination with the AXI Ethernet Lite IP Core (V3.0 of the core & Vivado 2020.1) the Ethernet Lite Core is configured to use AXI4LITE. This works fine with the AXI Traffic Generator. However, the moment I attach the core to a custom AXI Master the core exhibits some strange behaviour in simulation. Attached a screen shot from simulation.


It can be seen that for some reason the internal signal write_in_prog is asserted directly when WValid and AWValid are asserted. Of course this needs to be 1 clock cycle later. In addition, BValid remains active even after BReady is deasserted. To me it looks like the clocking of the core is somehow incorrect. There are no warning or so present during validation of the design. In addition, the clock seen in the plot looks good to me.

Any ideas?





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Registered: ‎05-21-2015

@mschokker ,

Unfortunately, the AXI interface to the AXI ethernet lite core is horribly broken and has been for some time.  While I haven't seen the bugs you mentioned above before, I have seen, verified, and reported other bugs in this core such as:

  1. Writes getting applied to the read address
  2. VALID/READY handshake violations.  RVALID should not be dependent upon RREADY.  This can cause a potential lockup, as shown in the following traceaxi_rvalidtrace.png
  3. AXI responses getting sent back to the wrong IDsaxi_rid.png
  4. Write packets getting dropped due to backpressure.write_backpressure.png
  5. RLAST getting applied to the wrong burstaxi_rlast.png

I first noticed these bugs about a year ago.  I last examined Vivado 2020.1 and they were still present.  I'm not sure when Xilinx intends to fix them.


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