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love119
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Registered: ‎03-08-2018

AXI UART IP Core with non AXI interface

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Dear All,

 

I'm trying to implement the UART and came cross Coregen tool can make UART IP for Xilinx FPGA but I think it's for AXI system not non-AXI system.

When I see that document, I'm not sure and can't find whether I can use AXI UART IP Core of Xilinx to non AXI interface.

If we can use it for non-AXI interface, Would you please help me what am I supposed to do ?

 

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hbucher
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Registered: ‎03-22-2016

@love119 The UART IP is exactly a wrapper to adapt the UART protocol to AXI.  If you want to use the UART protocol directly, there are easier ways like this

https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html

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hbucher
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@love119 what non-AXI protocol are you using?

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love119
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Registered: ‎03-08-2018
I meant that I 'd like to use just like directly interfacing the AXI UART IP without AXI BUS system.
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hbucher
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Registered: ‎03-22-2016

@love119 The UART IP is exactly a wrapper to adapt the UART protocol to AXI.  If you want to use the UART protocol directly, there are easier ways like this

https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.

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