AXI UART IP Core with non AXI interface

[love119]

Dear All,

I'm trying to implement the UART and came cross Coregen tool can make UART IP for Xilinx FPGA but I think it's for AXI system not non-AXI system.

When I see that document, I'm not sure and can't find whether I can use AXI UART IP Core of Xilinx to non AXI interface.

If we can use it for non-AXI interface, Would you please help me what am I supposed to do ?

[hbucher]

@love119 what non-AXI protocol are you using?

[love119]

I meant that I 'd like to use just like directly interfacing the AXI UART IP without AXI BUS system.

[hbucher · Accepted solution]

@love119 The UART IP is exactly a wrapper to adapt the UART protocol to AXI.  If you want to use the UART protocol directly, there are easier ways like this

https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html