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Adventurer
Adventurer
1,464 Views
Registered: ‎05-11-2018

AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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Hello,

 

I am trying to adapt this tutorial: https://www.xilinx.com/video/technology/dma-for-pci-express.html

I will be using the VC707 board and my goal is to write on the DRR3 memory using the MIG and a VHDL module that will issues the write commands as well as the words to write, then once the DDR3 memory is full i want to send all the data to a PC using the DMA PCI express IP.

I'm using VIVADO 2017.4 and i created a block design.

I added the MIG ip as well the DMA PCI EXPRESS BRIDGE IP, i clicked on run connection automation.

The interfaces of the MIG and DMA pci express are now connected via the AXI interconnect IP:

So the goal is to write on the MIG using a custom IP that i will create and reading the MIG using the DMA PCI express IP, therefore i added another slave interface to the AXI INTERCONNECT IP so i can connect it to my custom IP.

My custom IP will be an AXI master controller.

With vivado a clicked on the "Create and Package New IP" and selected the "Create AXI4 Peripheral" option.

I added a slave interface and an master interface. My aim is to connect the master interface to the slave interface that i add on the AXI interconnect module.

I tried to modify the VHDL file of the custom IP to change the width of the signals but errors occur.is

on the diagram pdf my custom Ip name is kais_0

I have also thought of not using a custom IP and just make external the S01_AXI_1 interface that i added on the AXI interconnect IP but again i face the same problem, i can't manage to match the S01_AXI_1 to the S_AXI interface ot the MIG.

Here is a pdf of the block diagramm that i created

Thank you for your help

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Adventurer
Adventurer
1,747 Views
Registered: ‎08-10-2017

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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Right-Click on C_M00_AXI_DATA_WIDTH ----> Select "Edit Parameter". The dialog box that appears is fairly intuitive.

You can choose 

  • to specify a list of values that are valid.
  • whether make the parameter editable.
  • a default value for the parameter.

When you create a master AXI interface, the tool generates a default code that

  1. writes numbers to an AXI slave,
  2. reads them back,
  3. checks if there is any mismatch between data written and data read.

You have to modify the code to make read and write state machines independent.

 

Seeing your block design, it is unclear to me as to why you created a slave AXI interface to your custom IP. You could've included your design in the custom IP itself, without the need to make the slave interface external (unless it is intentionally designed that way)

 

8 Replies
Explorer
Explorer
1,437 Views
Registered: ‎03-28-2016

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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It's likely that the IP Packager doesn't support generating an IP template with an AXI port that has a data width of 512 bits.  Try a more typical value such as 32 or 64.  It is very rare for an IP to use a data width as wide as 512 bits.

 

The MIG has a data width of 512, but your IP doesn't need to be that wide.  Instead, the AXI Interconnect will handle the size conversion between an IP's data width (32, 64) to the MIG data width (512).

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
Adventurer
Adventurer
1,748 Views
Registered: ‎08-10-2017

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

Jump to solution

Right-Click on C_M00_AXI_DATA_WIDTH ----> Select "Edit Parameter". The dialog box that appears is fairly intuitive.

You can choose 

  • to specify a list of values that are valid.
  • whether make the parameter editable.
  • a default value for the parameter.

When you create a master AXI interface, the tool generates a default code that

  1. writes numbers to an AXI slave,
  2. reads them back,
  3. checks if there is any mismatch between data written and data read.

You have to modify the code to make read and write state machines independent.

 

Seeing your block design, it is unclear to me as to why you created a slave AXI interface to your custom IP. You could've included your design in the custom IP itself, without the need to make the slave interface external (unless it is intentionally designed that way)

 

Adventurer
Adventurer
1,398 Views
Registered: ‎08-10-2017

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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You have to modify the code to make read and write state machines independent.

 

Be extremely careful when you modify the code. You  should still follow AXI protocol. Use AXI Protocol Checker, AXI Verification IP (http://www.wiki.xilinx.com/Validating+a+master+AXI4+interface+using+the+Verification+IP+as+a+slave) to verify if your AXI controller is working properly.

Adventurer
Adventurer
1,364 Views
Registered: ‎05-11-2018

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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@tedboothThanks for the answer,

If my Ip has a data width of 32 and the MIG has a data width of 512 how should i present the 512 bit word that i want to write on the MIG on the master interface of my IP.

Should i issue 16 write commands of 32 bits words?(16*32=512)

I don't understand how the AXI interconnect handles the conversion.

 

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Adventurer
Adventurer
1,353 Views
Registered: ‎08-10-2017

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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I suggest you use one write command with INCR burst of 16 words of each 32 bit ( AWBURST = 1, AWLEN = 15, WSTRB = all 1s).

Adventurer
Adventurer
1,347 Views
Registered: ‎05-11-2018

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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Thanks,

 

How should i write the 512 bits word on the 32 bits wide data bus?

If i issue only one write command i suppose the content of the 512 bits wide MIG word will be a concatenation of 16 times the word i presented on the 32 bits wide data bus of my IPs master interface.

I am reading the AMBA AXI and ACE Protocol Specification document http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf.

Is there another document that would better apply to what i am trying to do?

 

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Adventurer
Adventurer
1,338 Views
Registered: ‎08-10-2017

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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The document is good.

 

This is mentioned in page 39.

 

Write data channel

During a write burst, the master can assert the WVALID signal only when it drives valid write data. When asserted, WVALID must remain asserted until the rising clock edge after the slave asserts WREADY. The default state of WREADY can be HIGH, but only if the slave can always accept write data in a single cycle. The master must assert the WLAST signal while it is driving the final write transfer in the burst.

 

 

Moderator
Moderator
1,279 Views
Registered: ‎06-14-2010

Re: AXI interface mismatch between MIG and custom IP via the AXI interconnect IP

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Hello @cassandra,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply in the thread.

 

Thanks in advance and have a great day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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