03-23-2018 02:50 PM
I'm looking for the LogicCORE IP AXI4-Lite IP Interface (IPIF), described in pg155-axi-lite-ipif.pdf. Our installed version is Vivado v2017.4 (64bit). I tried looking in the IP integrator and the Language Templates, but do not see the IP. Can anyone point me to the its location?
03-24-2018 09:07 AM
If you're trying to create a custom IP to shim to your own non-AXI-lite ip, use the create and package IP interface in vivado. See UG1118, starting with the section on creating a new AXI4 peripheral.
For reasons I do not understand, IPIF is hidden in the gui. Find vv_index.xml in your install path.
<IP> <VLNV value="xilinx.com:ip:axi_lite_ipif:3.0"> </VLNV> <DisplayName value="AXI Lite IPIF"> </DisplayName> <Description value="AXI Lite IPIF"> </Description> <ProductGuide value="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_lite_ipif;v=v3_0;d=pg155-axi-lite-ipif.pdf"> </ProductGuide> <VersionInfo value="doc/axi_lite_ipif_v3_0_changelog.txt"> </VersionInfo> <HideInGui value="true"> </HideInGui> <CoreRevision value="4"> </CoreRevision> <ComponentPath value="xilinx/axi_lite_ipif_v3_0/component.xml"> </ComponentPath> <Taxonomies> <Taxonomy value="/BaseIP"> </Taxonomy> </Taxonomies> <AutoFamilySupport value="Level_2"> </AutoFamilySupport> <VendorURL value="http://www.xilinx.com"> </VendorURL> </IP>
You could try to set that to false. But then you get a worthless piece of IP in your sources, that you cannot customize, and no instantiation template. My guess is there is some hole in the documentation creation scripts used at Xilinx, and that this IPIF IP is not intended to be used directly.
See UG1118 instead.
03-26-2018 04:55 AM - edited 03-26-2018 04:56 AM
i was searching for this too last week and ending up writing my own wrapper RTL.
So the other solution would be to write your own AXI4Lite interface logic (glue logic code).
It is not difficult and for an experienced engineer shouldn't take more than a day to design and test it.
03-28-2018 09:14 AM
Thanks for the suggestions. I ended up following "Creating a New AXI4 Perifpheral" from chapter 3 of U1118 to create an AXI interface block in Verilog. Then I modified it to add what I needed. My guess is that IPIF has been replaced by this feature. Not sure why they are still updating the IPIF document.