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Visitor
Visitor
5,726 Views
Registered: ‎08-17-2011

About ISE schematic

please i need help on this warning:

 

WARNING:DesignEntry:243 -  ".sch" The user defined symbol '   ' has the same name as a Xilinx defined schematic symbol for device 'virtex' The Xilinx definition of the component will be used in your design. This may result in pin mismatches or functional differences in your design. If you did not intend to use the Xilinx component definition, please rename the user defined symbol.

 

 

I did not found anything of this kind of warning on internet?

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Scholar
Scholar
5,722 Views
Registered: ‎02-27-2008

e,

And why look on the internet?

The message is telling you "you have named something by a name that is already used"

What do you not understand? The name is already used for something. Did you intend to over-ride the name's definition? If so, fine. You are warned. If you know what you are doing, then continue.

If you did not intend to name it the same name, then name it a different name.
Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor
Visitor
5,719 Views
Registered: ‎08-17-2011

Thank you for the reply, but this is the fact, i don't now how to rename that symbol.

 

P.S. The symbol is edited by me and if i rename it in my working directory the same warning appears?

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Xilinx Employee
Xilinx Employee
5,696 Views
Registered: ‎07-22-2008

The symbol name should match the underlying schematic (or HDL or netlist file ) name.

The easiest thing to do is to rename the underlying schematic and then generate a new symbol for it.

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Visitor
Visitor
5,657 Views
Registered: ‎10-28-2011

Thee is an odd bug in ise that gets odder with time. Up to version 6, when you forgot to assign a .sch or .vhd file to

a symbol, it would tell you this as soon as you tried to compile.  Starting with version 7, it waits until Map. Clearly

it cannot generate a proper vhdl file if it does not know what is going on so synthesis has a bug.  The odd part is

that version 13 will kind of function in that it will pick something to use and not complain particularly about it. But

odd things happen with the final result. 

What is even more annoying is that it will decide it likes a certain type of file and refuse to let go of that one. I have

been converting some of my older files from .sch to .vhd but even if you replace the .sch with a .vhd in the

design hierarchy, it still will use the .sch file.  The only way you can stop that is to actually delete the .sch

file.

Note that this cannot be fixed with the cleanup project files since you have to do that before every compile

because of other bugs and it is still present.

I wish that xilinx would go back to service packs where we at least had some hope of getting a vaguely

functioning version before they put in new bugs for us to fight.