11-13-2015 04:47 PM - edited 07-25-2016 07:49 PM
Design Entry is done with the Hardware Description.
Languages that do that are :
- Verilog and VHDL
- or also graphical means such as the schematic editor or others.
My question is how accurate are they, sorry if I need to be corrected but I tried very hard and without success to
describe one single slice.
The idea is to have one state machine that will be synthesised in one single slice
both LUT and Flip Flops would be utilized
does anyone have an example that works?
when I just describe the LUT and FF it then synthesises all over the place so there is the need to constrain to an area and the precise slice, anyone with experience to do that?
Many great thanks
11-15-2015 10:36 AM
You can try LOCing the LUT and register in that particular slice.
set_property BEL B6LUT [get_cells LUT3_inst]
set_property LOC SLICE_X411Y550 [get_cells LUT3_inst]
set_property BEL B5FF [get_cells FDRE_inst]
set_property LOC SLICE_X411Y550 [get_cells FDRE_inst]
11-25-2015 10:47 PM
If you or anyone has a design that synthesises in exactly one slice it would be neat to see how its done
It would inspire designs that are bitslice oriented and where the local logics would be good to have packed in a slice or a couple of ones so the internal triggers are real fast and then the array of it would not care of the lags because the design would "avalanche" the slice(s) results
There if someone could help that would be neat, its a bit like trying to have the "optimum" of all the designs and use it as base so one is always trying to stay close for the best yield?
Someone correct me if I'm overseeing something
Cheers and many thanks to all that make this technology available to all
and open the door to the wonderfull prospects of ideas that can come true
Thanksgiving wishes to all that are carrying hard labor and skills