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Explorer
Explorer
7,904 Views
Registered: ‎09-02-2009

Accurate Design Entry for 1 single slice

Design Entry is done with the Hardware Description.

Languages that do that are :

 

- Verilog and VHDL

- or also graphical means such as the schematic editor or others.

 

My question is how accurate are they, sorry if I need to be corrected but I tried very hard and without success to

describe one single slice.

 

The idea is to have one state machine that will be synthesised in one single slice

 

both LUT and Flip Flops would be utilized

 

does anyone have an example that works?

 

when I just describe the LUT and FF it then synthesises all over the place so there is the need to constrain to an area and the precise slice, anyone with experience to do that?

 

Many great thanks

 

thanks everyone for the amazing help
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3 Replies
Xilinx Employee
Xilinx Employee
7,865 Views
Registered: ‎02-16-2014

Re: Accurate Design Entry for 1 single slice

Hi @p94100687

 

You can try LOCing the LUT and register in that particular slice.

For example,

 

set_property BEL B6LUT [get_cells LUT3_inst]
set_property LOC SLICE_X411Y550 [get_cells LUT3_inst]
set_property BEL B5FF [get_cells FDRE_inst]
set_property LOC SLICE_X411Y550 [get_cells FDRE_inst]

 

Xilinx Employee
Xilinx Employee
7,806 Views
Registered: ‎02-16-2014

Re: Accurate Design Entry for 1 single slice

hi @p94100687

 

Are you able to LOC them in same slice now?

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Explorer
Explorer
7,776 Views
Registered: ‎09-02-2009

Re: Accurate Design Entry for 1 single slice

Hi 

 

If you or anyone has a design that synthesises in exactly one slice it would be neat to see how its done

 

It would inspire designs that are bitslice oriented and where the local logics would be good to have packed in a slice or a couple of ones so the internal triggers are real fast and then the array of it would not care of the lags because the design would "avalanche" the slice(s) results

 

There if someone could help that would be neat, its a bit like trying to have the "optimum" of all the designs and use it as base so one is always trying to stay close for the best yield?

 

Someone correct me if I'm overseeing something

 

Cheers and many thanks to all that make this technology available to all

and open the door to the wonderfull prospects of ideas that can come true 

 

Thanksgiving wishes to all that are carrying hard labor and skills

 

thanks everyone for the amazing help
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