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Observer cerg19
Observer
20,248 Views
Registered: ‎07-12-2012

Add vhdl file in Vivado diagram

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Hi.

 

I create simple project from Xilinx IP in Vivado 2013.4. I add all IP in Diagram and connect them to each other. I create custom vhdl file and want to add this file as component in diagram and connect it to others IP.

 

How I can create schematic block from my vhdl file and add it to my diagram?

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Xilinx Employee
Xilinx Employee
32,540 Views
Registered: ‎09-20-2012

Re: Add vhdl file in Vivado diagram

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Hi,

 

Package your design using Vivado IP packager. After this add the IP repository to your block design project IP catalog. After this you can see your custom IP in "ADD IP" of block design.

 

Check these for more details

 

chapter-8 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf

lab-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug939-vivado-designing-with-ip-tutorial.pdf 

 

Thanks,

Deepika.

Thanks,
Deepika.
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7 Replies
Xilinx Employee
Xilinx Employee
32,541 Views
Registered: ‎09-20-2012

Re: Add vhdl file in Vivado diagram

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Hi,

 

Package your design using Vivado IP packager. After this add the IP repository to your block design project IP catalog. After this you can see your custom IP in "ADD IP" of block design.

 

Check these for more details

 

chapter-8 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug896-vivado-ip.pdf

lab-3 of http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug939-vivado-designing-with-ip-tutorial.pdf 

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
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Observer asrarhashmitud
Observer
18,485 Views
Registered: ‎07-23-2014

Re: Add vhdl file in Vivado diagram

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Hello,

 

I want to ask further on this. I got the point that we can at custom vhdl after packaging and all that.

My question is that my vhdl is under designing/testing phase so every time i have to re package it and then re instantiate it which takes a lott of t ime. Does there exist any simpler way for doing this?

 

tHanks

Asrar

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Visitor m.alkadi
Visitor
12,913 Views
Registered: ‎04-22-2016

Re: Add vhdl file in Vivado diagram

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Hi,

 

I have this problem as well. Actually, in GUI mode Vivado can detect changes in the source files. The IP can be then updated with a couple of clicks without repackaging. But I didn't find a solution in tcl mode.

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Observer caryan
Observer
11,059 Views
Registered: ‎04-17-2014

Re: Add vhdl file in Vivado diagram

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For other internet searchers out there, as of Vivado 2016.1 it is much easier to add a bare HDL file to a block design by adding a module rather than jumping through hoops to package it up as IP. Vivado does a decent (but not perfect) job of just inferring the interfaces. See "Chapter 12: Referencing RTL Modules" in UG994.

Contributor
Contributor
10,750 Views
Registered: ‎03-04-2009

Re: Add vhdl file in Vivado diagram

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But beware!!!

If you happen to have instantiated some IP module in that RTL code, you will get an error telling you that referencing of IP is not enabled.

 

I have also had little luck with RTL files instantiating components in .ngc files. They pass synthesis, but fail on implementation with the message that they are black boxes, and vivado cannot find the underlying instance.

 

A vivado project with plain RTL toplevel (not block diagram) would find those .ngc files

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Observer caryan
Observer
10,533 Views
Registered: ‎04-17-2014

Re: Add vhdl file in Vivado diagram

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Yeah, there is a long list of limitations:

 

• The RTL module definition cannot include other IP definitions (XCI), netlists (EDIF or
DCP), nested block designs (BD) or another module that is set as out-of-context (OOC)
inside the RTL module.
• VHDL and Verilog are the only supported languages for module definition.
TIP: SystemVerilog and VHDL 2008 are not supported for the module or entity definition at the
top-level of the RTL module. 

We ran into the ngc one too as it's not explicitly listed but I assume it falls under the no netlists limitation and the VHDL-2008 is another annoying limitation for us.

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Explorer
Explorer
1,900 Views
Registered: ‎12-07-2018

Re: Add vhdl file in Vivado diagram

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Thank you very much for this post and the solution. 

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