03-13-2015 04:39 PM
I need to implement a bank of large FIR filters that use complex valued coefficients. FFT flltering is ideal for such filters but I am finding it laborious to implement these functions using strait VHDL. All the Xilinx DSP cores have now been rewritten with AXI-Stream interfaces which does not help matters. All this AXI-fication is intended to help us so I am thinking perhaps i must be taking the wrong approach.
Should I be using the Vivado IP Integrator for such a design?
About half the blocks in the design are IP cores and about half will be custom cores that I will have to write.
I realize this is a very general question but I am soliciting advice. If there are others who have done similar designs using IPI I would like to hear from them.
03-13-2015 04:54 PM
I'll argue the opposite. You'll get more bang-for-the-buck, and more flexiblity doing it yourself in RTL.
A 1-D FIR is not complicated. The testbench for it is not complicated either. (It's easy to create a "golden" model for your data). Just roll your own with whatever features you need. Optimize to your needed level.
I'd just recommend doing it ONCE - create a shared module which you can instaciate in multiple places, with multiple (possibly different) configurations.
Then you can take it with you wherever you go, and not be slave to random updates and features you don't need.
I've NOT really used the the Vivado IPI much. Tried it once - that was enough. As I just said in another thread, such wizards take "Dead-Simple things, and make them... Dead-Simple with a GUI". At the same time, becoming an opaque mess for anything slightly above "Dead-Simple".
(Ranted twice on the same thing in the same day.. Must be the daylight savings...)
03-13-2015 05:35 PM
03-14-2015 08:52 AM - edited 03-14-2015 08:58 AM
While I can respectfully appreciate the point that Mark is making which is certainly valid in some cases, I think IPI may actually help you for your specific needs.
One of the main advantages to IPI (IMO) is that it abstracts the connection of interfaces for you. Have you ever tried to connect an AXI Interconnect to multiple devices in HDL? It takes forever and it's error prone to do by hand. In IPI, it's a button click.
The fact that most Xilinx IP are now AXI is not a mistake/coincidence. When combined with a tool like IPI, it becomes very easy to rapidly connect one block to the next because they all have the same standardized interfaces. Further, it is very easy to integrate your own custom IP blocks. IPI can automatically infer interface types from your custom HDL (not just AXI Stream... many interfaces are natively supported and you can even create your own!).
At the end of the day, I think what you're really asking for is some kind of abstraction. You could accomplish this by learning some higher level language features (use records to create interfaces, generate-for to create mutliple instances of the same code without copy-pasting, systemverilog, etc) and/or by taking advantage of higher level tools such as IPI. Each will have its own advantages/disadvantages and both will have somewhat of a learning curve.
03-16-2015 09:48 AM
Whatever solution you take - sounds like a fun project.
03-27-2015 08:16 AM
Thanks for the input.
I am about half way through entering my design in strait VHDL. It has been a lot of ripping and packing of AXI Streaming interfaces.
I was really hoping that HLS would work so that I could walk upright but it is very fragile when used with FFT cores.
Next, I tried using the VHDL ieee_proposed.fixed_pkg library to get some decent data types but it is not compatible accross simulation and synthesis.
I hesistate to adopt IP Integrator because it is a Xilinx proprietary tool with a steep learning curve. Other than Xilinx employees, I don't see a lot of enthusiasm for IPI streaming designs.