I've seen a few other posts having the same problem as me so I'm assuming this is a bug. Just thought I'd document my experience here. Sorry if this is the wrong forum section for this.
I have created an IP core using Vivado HLS, I'll call it "test_ip". This test_ip uses an AXI_Stream interface on the input and output with the TLAST side channel signal included. My project target language is VHDL. I have imported my test_IP into a block design (called "design_1") that I have set up to test it. When I attempt to run behavioral simulation, I get the following two errors:
[VRFC 10-619] entity port strm_in_tlast does not match with type std_logic_vector of component port
[VRFC 10-619] entity port strm_out_tlast does not match with type std_logic_vector of component port
These errors pertain to my IP's VHDL file: test_ip.vhd. In test_ip.vhd (the file created by Vivado HLS), strm_in_tlast and strm_out_tlast are of type std_logic. In design_1_test_ip_0.vhd (the wrapper created by IP integrator?), they are of type std_logic_vector(0 downto 0).
I'm not sure if this is a bug with Vivado HLS creating the ports with the wrong type that Vivado is expecting, or Vivado creating the wrapper around the HLS file wrongly.
Anyways, to workaround the problem I just switched my project target language to Verilog and regenerated the output products.