cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Newbie
Newbie
390 Views
Registered: ‎05-01-2019

Anybody used the 'xport' tool converting ABEL to Verilog?

I took an old ABEL file (.abl) which I use with the old ISE 10.1 software and converted it to a Verilog file (.v) using 'xport' so I could use the later ISE 14.7 software (14.7 doesn't support ABEL code).  I compiled the ABEL file using 10.1 (which we actually use in our products) and then I compiled the converted Verilog file using 14.7.  I noticed the two compiled .jed files are totally different (bit patterns are totally different in a number of cases), but only 6 bytes different in length.  I'm pretty good with ABEL, but not so good with Verilog.  Is there a way to compare two .jed files to see whether the files are in fact the same functionality?  I can't imagine the files being so different is just an efficiency difference.

 

Sutton

0 Kudos
1 Reply
Highlighted
Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎05-14-2008

Re: Anybody used the 'xport' tool converting ABEL to Verilog?

It is possible that the .jed files generated from ISE 10.1 based on ABEL and from 14.7 based on Verilog.

ISE only guarantees that when the source files, constraint files, software version and process options are all not changed, the final result is the same.

I suggest you verify the Verilog design in ISE 14.7 by simulation and on board testing.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos