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Explorer
Explorer
4,680 Views
Registered: ‎08-26-2014

Are these two block diagrams correct and have different speed access to the BRAM?

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Hello,

 

I have seen a block design using Vivado version 2014.3 where when using the two AXI Master ports (M_AXI_GP0 and M_AXI_GP1) to connect two Block RAM controllers, it uses two AXI Interconnect blocks like in the next diagram:

 

AXI_master 1.png

 

However, with Vivado 2016.3 and using the Connnection Automation, it groups the two AXI Interconnect blocks together like shown in the next picture:

 

AXI_master 2.png

 

I don't know if this new version of Vivado (2016.3) groups all the AXI Interconects in the same block to make the visualization of the diagram easier or these two implementations are both possible and differ in speed access to the BRAM.

 

Thanks,

 

Cerilet

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Teacher muzaffer
Teacher
8,710 Views
Registered: ‎03-31-2012

Re: Are these two block diagrams correct and have different speed access to the BRAM?

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@cerilet Yes these two connectivities are both possible but the second one is redundant. Normally you would do this if both master wanted/needed access to both slaves. But the address ranges of GP0 & GP1 don't overlap so there is no way for them to access to both memory blocks so you would be wasting all the logic which manages overlaps between two masters. Either use the first option or connect both memories to the same GP port (in which case make just one larger memory)

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Teacher muzaffer
Teacher
8,711 Views
Registered: ‎03-31-2012

Re: Are these two block diagrams correct and have different speed access to the BRAM?

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@cerilet Yes these two connectivities are both possible but the second one is redundant. Normally you would do this if both master wanted/needed access to both slaves. But the address ranges of GP0 & GP1 don't overlap so there is no way for them to access to both memory blocks so you would be wasting all the logic which manages overlaps between two masters. Either use the first option or connect both memories to the same GP port (in which case make just one larger memory)

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Explorer
Explorer
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Registered: ‎08-26-2014

Re: Are these two block diagrams correct and have different speed access to the BRAM?

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Thanks @muzaffer. It was just a test circuit.

 

I was in doubt because the first option was giving me an "address memory assignement error". I finally got it working using tcl commands to assing the proper addresses.

 

Cheers!

 

Cerilet

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