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Observer altameemi
Observer
13,303 Views
Registered: ‎05-21-2009

Arithmetic Shift

Hi All

As Xilinx instruct in ISE language templates that operator "<<" to operate a left logical shift and this on "<<<" to operate a left Arithmetic shift. But when I used both of them, I got a logical shift in both cases. I use ISE 12.4. Is there some thing with my code.

I will be highly appreciated if some body guide.

Regards

 

alwayes ...

.

.

sh_result[31:16] <= sh_in >> 6;  //Do a logical shift

sh_result[31:16] <= sh_in >>> 6; // Should give an Arithmetic shift, but it doesn't (the result as in previous expression)

 

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5 Replies
Professor
Professor
13,291 Views
Registered: ‎08-14-2007

Re: Arithmetic Shift

Unless your variables are signed, then a logical shift and arithmetic shift

should give the same results.  Using signed logic is tricky in Verilog.

mixed operations tend to default to using unsigned arithmetic, rather

than the expected signed arithmetic.  How did you define sh_in?

 

-- Gabor

-- Gabor
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Historian
Historian
13,278 Views
Registered: ‎02-25-2008

Re: Arithmetic Shift

 


gszakacs wrote:Using signed logic is tricky in Verilog.

mixed operations tend to default to using unsigned arithmetic, rather

than the expected signed arithmetic. 

 

-- Gabor


 

That's why Verilog is the best HDL ever invented, or that will ever be invented.

 

;)

----------------------------Yes, I do this for a living.
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Observer altameemi
Observer
13,262 Views
Registered: ‎05-21-2009

Re: Arithmetic Shift

Hi Gabor

I have actually cheked the above operators (>> and >>>) individually. sh_in is the input data, which should be shifted. sh_in is provided from many registers located in a registers file. The supplied data was contain a 1 in MSB, which should refer to the sign bit, shouldn't it ? If not, how can I assign signed and unsigned binary patterns please?

Thanks

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Instructor
Instructor
13,259 Views
Registered: ‎07-21-2009

Re: Arithmetic Shift

From the Stuart Sutherland Verilog (2001) HDL Quick Reference Guide:

 

operator   example   description

  >>>      m >>> n   shift m right n-times; fill with value of sign bit if
                     expression is signed, otherwise fill with 0 (Verilog-2001)

 

   >>      m >> n    shift m right n-times and fill with zeros

 

If the variable being shifted is unsigned, the operator >> is entirely equivalent to the operator >>>.

The supplied data was contain a 1 in MSB, which should refer to the sign bit, shouldn't it ?

Only if the data type of the variable being shifted is declared as signed.  If unsigned, an arithmetic right shift will fill with '0'.  You should re-read Gabor's post, I am merely repeating what Gabor has already written.

 

By the way, if you are interested in Verilog training or are interested in a Verilog book, Stuart Sutherland is an excellent instructor (and author).  I've taken his workshop.

 

-- Bob Elkind

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Observer altameemi
Observer
13,189 Views
Registered: ‎05-21-2009

Re: Arithmetic Shift

Thank you very much for your detailed explanation guys.

 

Cheers

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