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Registered: ‎01-29-2020

Artix-7 Aurora 8b10b Error During Implementation-Placement Phase

Hello Everybody,

First of all I should specify that I've searched the related posts for my problem. And there were two different posts that have solution labels. However, those recommended solutions unfortunatelly does not solve my problem.

Now, let me explain what kind of problem I'm experiencing during implementation. But, indicating to some design properties will be informative and useful for anyone who reads this post as a starting point.

Tool Version : Vivado 2016.4

Target Device: xc7a100-2tfbg484

Block Design Configuration#1 : uBlaze + AXI-Interconnect + AXI Chip2Chip + Aurora 8b10b

Block Design Configuration#2 : uBlaze + AXI-Interconnect + AXI Chip2Chip + [1G/2.5G Ethernet Subsystem (in SGMII mode) + FIFO] + Aurora 8b10b

Design Purpose: And data comes from ethernet will be send to target FPGA through 1-Lane Aurora or vice versa.

In block design I've tried two different design configurations as I specified above. First configuration has been implemented without any error and time slack. On the other hand, second configuration has failed at the placement phase of implementation.

By the way, anyone who wants to see the block design connection and some more details for the problem can has a look at the following link:

https://forums.xilinx.com/t5/Implementation/aurora-8b10b-implementation-fails-after-customizing-block-bug/m-p/1070601/highlight/true#M27298

Configuration#2 generates following errors:

1)

Text_Error.PNG

2) A LUT2 cell in the design is missing a connection...

For the second error, in UG904 under "Common Design Errors" title this problem is being addressing. And it is said that this kind of errors might be sourced because of undriven ports. This is a correct indicator for the problem. When I searched any undriven port for aurora ip, I found drp_add/data ports in floating position. However, I don't need these port connections and during the block design phase Aurora IP didn't bring these signal ports excep drp_clk. And somehow block design validation makes the  drp_clk port connection mandatory. But at the implementation step this undriven port error occurs. When I applied the offered solutions (in UG904) that are basen on design optimisation tcl commands don't corrects given error.

For the first error, I do not have any idea where/why it occurs.

Could you please help on this issue?

In addition, can anyone recommend a dual port fifo connection for the aurora connection in block design?

 

Thanx in advance for any comment and/or recommendation,

Best Regards.

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