I would like to create an automated design using CMake that can peform an FPGA implementation from opening the Vivado to the bitstream generation. I already have seen some examples used CMake for Vivado_HLS which its output is a .sln solution file. Is there a way to do it the same for Vivado designs including IP cores, block designs, and HDL codes using CMake?
It is very much appreciated if someone could provide a simple example in this regard, if any. Thanks a lot.