Automatic Zynq PS DDR & System Pin Placement in PlanAhead
I've got a Zynq PS configured in PlanAhead for an xc7z030 that was based off a previous design for a xc7z020. I take the project through synthesis and it seems PlanAhead does a good job in auto placing the PS DDR signals correctly - except for the clk diff pair. Also, the PS clk, PORB, and SRSTB pins aren't auto placed. I also can't seem to manually select the correct IO pin as they're an invalid option. Any guesses?