09-16-2016 07:06 AM
Using Vivado 2015.4
The bd looks like this :
Now I get this critical warning :
now the design synthesises, but I don't like this critical warning. How can I solve this?
Must I output a 32 bit address from my custom IP? I could just fill up the uppr 32 bits with zeroes, but in that case I must make sure that the address lines from my custom IP match the size setting of the dual port ram in the address editor. As i did it now, I can visually check this in the block diagram (and I even get a nasty warning :-)
09-16-2016 10:53 AM
09-16-2016 06:20 PM
09-22-2016 07:26 AM
My issue is this :
after setting the memory size in address editor to 4k (4096 bytes) (2^12 address lines needed), and pressing validate design, the BRAM controller correctly picks up this size : it limits the bram_addr_a to [11:0]
however I get this warning :
WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(12) - Only lower order bits will be connected.
On the PORT B I have connected a custom IP, that also only outputs 12 address lines, and is connected the addrb[31:0]
Now I even get a 'critical warning' :
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/blk_mem_gen_0/addrb'(32) to net 'MyIp_0_BRAM_addra'(12) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Question 1 : do I need to worry about these 2 warnings?
Question 2 : how can I avoid these warnings?
i.e. for PORT B I could concatenate 'zeroes' on top of the 12 address bits in the block design I guess, but that's uggly. Or I could adjust MyIP to output 32-bit addresses, but with bits [31:13] set to '0' . But I'm just wondering why the BRAM controller picks up the size from the address editor, but the blk_mem_gen doesn't...