UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Advisor ronnywebers
Advisor
5,798 Views
Registered: ‎10-10-2014

BD 41-1228 mismatch on address bus of BRAM

Using Vivado 2015.4

 

  • I've instantiated a dual port ram in my block design, PORT A connects to a axi_bram_ctrl, PORT B connects to a custom IP.
  • I've set the size of the dual port ram in the address editor to 4k, that should correspond to 12 address lines on the BRAM ports. 
  • Now my custom IP outputs a 12 bit address as it should, which I want to connect to the 12 bit addr on port B of the dual port ram
  • However the blk_mem_gen_0 block shows an address port addrb[31:0] of 32 bits, regardless of the 4k setting in the address editor.

 

The bd looks like this :

 

bram - bd.png

Now I get this critical warning :

 

bram addr mismatch - warning.png

 

now the design synthesises, but I don't like this critical warning. How can I solve this?

 

Must I output a 32 bit address from my custom IP? I could just fill up the uppr 32 bits with zeroes, but in that case I must make sure that the address lines from my custom IP match the size setting of the dual port ram in the address editor. As i did it now, I can visually check this in the block diagram (and I even get a nasty warning :-)

 

 

 

 

 

 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
5,779 Views
Registered: ‎08-01-2008

Re: BD 41-1228 mismatch on address bus of BRAM

check example . you can example in Vivado

check this ARs as well
http://www.xilinx.com/support/answers/63041.html
check this post
https://forums.xilinx.com/t5/Design-Entry/How-to-interface-AXI-BRAM-Controller-with-Block-Memory-generator/td-p/636843
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Teacher muzaffer
Teacher
5,772 Views
Registered: ‎03-31-2012

Re: BD 41-1228 mismatch on address bus of BRAM

one option is to switch to standalone mode in the block memory generator and fill in all the numbers yourself. Whether this is more less error-prone is open to debate.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Advisor ronnywebers
Advisor
5,694 Views
Registered: ‎10-10-2014

Re: BD 41-1228 mismatch on address bus of BRAM

thanks @balkris,

 

  • the first link seems to be less related to my issue, I don't get all the details there, it seems to go way beyond my issue
  • the 2nd link is understandable, but is also not my issue - the guy had an issue with word vs byte addresses.

 

My issue is this :

 

 PORT A

after setting the memory size in address editor to 4k (4096 bytes)  (2^12 address lines needed), and pressing validate design, the BRAM controller correctly picks up this size : it limits the bram_addr_a to [11:0]

 

however I get this warning :

 

WARNING: [BD 41-235] Width mismatch when connecting pin: '/blk_mem_gen_0/addra'(32) to net 'axi_bram_ctrl_0_BRAM_PORTA_ADDR'(12) - Only lower order bits will be connected.

 

 

PORT B

On the PORT B I have connected a custom IP, that also only outputs 12 address lines, and is connected the addrb[31:0]

 

Now I even get a 'critical warning' :

 

CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/blk_mem_gen_0/addrb'(32) to net 'MyIp_0_BRAM_addra'(12) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.

Question 1 : do I need to worry about these 2 warnings?

Question 2 : how can I avoid these warnings?

 

i.e. for PORT B I could concatenate 'zeroes' on top of the 12 address bits in the block design I guess, but that's uggly. Or I could adjust MyIP to output 32-bit addresses, but with bits [31:13] set to '0' . But I'm just wondering why the BRAM controller picks up the size from the address editor, but the blk_mem_gen doesn't...

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos