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Visitor andyionscope
Registered: ‎07-14-2014

[BD 41-951] Parameter LAYERED_METADATA not found

I am working with the Microblaze and some custom IP blocks (one with an AXI-Lite interface). After entering the blocks into a block diagram and run Validate design, I get the following error message 6 times.


[BD 41-951] Parameter LAYERED_METADATA not found on /rst_clk_wiz_1_100M/peripheral_aresetn


The design builds correctly (synthesis/route/generate bitstream etc) and the code that I run on the Microblaze runs correctly, but I am concerned about the meaning of the error message.


I have searched the forum and the internet in general, but I can not find any reference to this error message. It seems to only occur when I connect my custom IP blocks to the peripheral reset line from the rst_clk_wiz_1_100M_0 block that is created with the Microblaze.


Any suggestions on what this error means and what the solution might be, I can post more details if required, but in the first instance, I was just looking for a reference to the error message to see what the cause might be?





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3 Replies
Registered: ‎07-08-2016

Re: [BD 41-951] Parameter LAYERED_METADATA not found

I Just got this error message as well. Anybody have an answer? It was from connecting a clock source to a shift ram register pipelining a signal output from an axi_fifo

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Teacher muzaffer
Registered: ‎03-31-2012

Re: [BD 41-951] Parameter LAYERED_METADATA not found

I have also seen this (critical) warning in my design. In my case it was related to connecting a signal of type clock to a BD port of type data. Changing the -type option of the create_bd_port command (to -type clk) fixed this issue. It's possible the net type of the signal you are using as a clock is not marked as a clock.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Visitor julenp
Registered: ‎02-13-2019

Re: [BD 41-951] Parameter LAYERED_METADATA not found


 I know that there are a lot of time that it´s thread was resolved.  But now, i have the "same" problem.

I´m going to explain my situation: i have two lvds ports, these signals goes to a lvds buffer which throw a single signal. This single signal goes to my own IP.

In my case: the ports have the clk type; the type of utility_ds_buf is clk also; the output of my single signal the same; and the last one,the entry of the IP has the clk type also...

I don´t know where is my problem.

Thanks you very much


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