cancel
Showing results for 
Search instead for 
Did you mean: 
266 Views
Registered: ‎08-21-2018

BD file synthesis failed

hi,

I used HLS to generate two IPs. These two IPs call the same function in the hls video library. (I used different variable names for the variables of the two IPs.) then two IP core added to the block design. The role of the two IPs is to handle the left and right video channels. Synthesizing the Block Design project, the following error message appears.{FX(AH99)FX9RWWZ5KI6Y@W.pngB[]R5GU4B[3X}0KTB%5Z1]8.png

thank you !!!

0 Kudos
2 Replies
Highlighted
Moderator
Moderator
243 Views
Registered: ‎03-16-2017

Re: BD file synthesis failed

Hi @zhang842709698 ,

Did you check those RTL and verify that those port connections are present or not? 

Similar issues i have found : 

https://forums.xilinx.com/t5/Synthesis/Block-design-named-port-connection-does-not-exist-in-block/td-p/828591

https://forums.xilinx.com/t5/Synthesis/quot-Synth-8-448-named-port-connection-clk-does-not-exist-quot/td-p/941955

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Highlighted
227 Views
Registered: ‎08-21-2018

Re: BD file synthesis failed

hi,

I am using the two IPs generated by HLS. the functions of the two IP cores are the same. And the two IP cores call the same function of the hlS library. (The variable names of the two IP cores are different.)Two IPs process the left and right video separately.

Adding one of the IP cores separately in the block design can be Synthesis success. But adding two IP cores to the block design at the same time can be Synthesis failed. I think my situation is not the same as the situation you mentioned above.

I hope you can help me solve.

0 Kudos