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Observer
Observer
1,469 Views
Registered: ‎11-27-2015

Bad .edn from write_edif vivado with divider

Hello,

 

With vivado I can create an IP a non blocking divider radix2.

Then I instantiate it with a top level  synthesis and implementation OK I can read the netlist deep down to the divider.

Then I write_edif to use this edif into synplify. But it seems this edn file is not complete since synplify recognize it deep inside it sees black box!!

Even with an edit file I can't see the instances I see in the original netlist of vivado.

I even tried to import this edn file into a new vivado project and same thing

 

 

Regards

Johann

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Moderator
Moderator
1,448 Views
Registered: ‎09-15-2016

Re: Bad .edn from write_edif vivado with divider

Hi @jhouee

 

Can you show us the difference between netlist after synthesis and netlist created by write_edif? Does your 'non blocking divider radix2' IP contains any Xilinx IP generated ooc?

It will be helpful if you can share the project to reproduce at our side and then debug.

 

Regards

Rohit

Regards
Rohit
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Observer
Observer
1,444 Views
Registered: ‎11-27-2015

Re: Bad .edn from write_edif vivado with divider

Hello,

 

My project zipped is 33Mbytes how can I send it to you ? Too big here for attachment i tried!

 

Regards

Johann

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Moderator
Moderator
1,442 Views
Registered: ‎07-01-2015

Re: Bad .edn from write_edif vivado with divider

Hi @jhouee,

 

I will share the attachment with Rohit @thakurr

 

Thanks,
Arpan
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Moderator
Moderator
1,423 Views
Registered: ‎09-15-2016

Re: Bad .edn from write_edif vivado with divider

Hi @jhouee

 

For Synplify you need to add the stub file of the Xilinx IP which will prevent insertion of IO buffers if IP is instantiated in the top level. This stub file will also infer black box for synthesis  in third party tool.

I would suggest you to refer the flow mentioned in below link, page 75 to work with third party synthesis tool.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug896-vivado-ip.pdf

 

I attached the edif both created in the Vivado and Synplify. You notice the difference in the two files with IP netlist is blackbox for top level in the third party edif.

 

Hope the shared info helps.

 

Regards

Rohit

Regards
Rohit
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Observer
Observer
1,351 Views
Registered: ‎11-27-2015

Re: Bad .edn from write_edif vivado with divider

Rohit,

 

Now it works with a.vm file only

 

In fact I synthesis with synplify my full design and add the .edf in vivado for the following place/route phase. It works fine except if I add the divider IP inside.

So I add the divider en file .edn plus verilog top file of it in synplify and created the final edn of my full design.

DW_div_seq.v

div_ip_vivado.edn (created from xci in vivado in a separate project before to use it in synplify)

div_ip_vivado.v

Then during the opt_design/place/route phase in vivado the divider is a black box. !

However if I add a .vm for my full design from synplify instead of .edf the full flow place/route is fine and take into account my divider !!!

 

Regards

Johann

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Moderator
Moderator
1,344 Views
Registered: ‎09-15-2016

Re: Bad .edn from write_edif vivado with divider

Hi @jhouee

 

In fact I synthesis with synplify my full design and add the .edf in vivado for the following place/route phase. It works fine except if I add the divider IP inside.

 

You need to add IP xci file in the Vivado post synth project or RTL project. xci file will contains IP output products including constraints which is applied after all netlist is combined (end user and IP).

Did you check the steps mentioned in the link shared before?

 

Regards

Rohit

 

Regards
Rohit
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Observer
Observer
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Registered: ‎11-27-2015

Re: Bad .edn from write_edif vivado with divider

Yes thanks !

 

for me ticket is solved !

 

Johann

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Moderator
Moderator
1,305 Views
Registered: ‎09-15-2016

Re: Bad .edn from write_edif vivado with divider

Hi @jhouee

 

Thanks for the response.

I am glad your issue is resolved. Please close the thread by marking appropriate post which helped you as solution. This will help other users in future incurring the same issue.

 

 

Regards
Rohit
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