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Visitor jarez95
Visitor
260 Views
Registered: ‎04-25-2019

Block Design Flow & .SV top fle

Hi,

I have been using the Red Pitaya (Zynq7010) for a while now and have developed some applications in c which use the GPIO and the SPI configuration, as defined in the classic FPGA bitstream and it works really well. I am now transitioning over to begin my own FPGA block design which will have this functionality and a lot more (involving the ADC's, DAC's and various FFT's which should be user controllable). I have loaded up the classic project and seen that it is quite resource hungry utilising about 25% of the available logic, I can see that this is spent on various functionality which I dont need, so I've simply commented this out in the top sv file, now I've got the utilisation down to about 3 or 4% and my c applications still work on this bitstream. I am thinking perfect I now just have to slap on my own ADC and DAC block designs based on various other projects and I should be good to go ?

However, simply adding blocks does not work as the .bd file is not at top, red_pitaya_top.sv is. Changing the top obviously doesnt work as the aforementioned file implements a great deal of the logic/wiring in .sv files and through others and relies on this strict hierarchy to do it properly. So I was thinking why not convert the design/project into its own ip and just import that into a new project, I also cant do that since it is written in sv and Vivado does not let you export ip with an sv top, it needs to be in verilog. I've seen some topics online about how to make a verilog wrapper for system verilog, through basically writing your own interface - but I am sceptical about how to implement this as I am worried I will interpret the connections wrongly and mess up the functionality of the system (it would also be very time consuming). If anyone has had success with this or knows how to, do let me know?

I've also tried building up the processing system exactly the same as the classic bitstream, but haven't got so far in this because I am not sure how can mirror the AXI, GPIO and SPI implementation, as a good portion of this is custom wired in sv. (GPIO - I could probably give it a go and get that to work).

I am also unsure about whether using the Xilinx SDK would be a good way to go right about now, before I start really learning about how to use Vivado block design flow properly, I've been keeping an eye on the projects in the community for a couple of years now, mainly Pavel, Anton and Koheron and they seem to have stuck with the block design flow, which I also find quite intuitive, so I am a bit reluctant to consider anything else.

If anyone has any pointers or advice, it would be greatly appreciated!

Best Regards, Renegade

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2 Replies
Scholar drjohnsmith
Scholar
251 Views
Registered: ‎07-09-2009

Re: Block Design Flow & .SV top fle

This seems a little specific to the re dpita board,

you might get more direct responce from the excelent https://forum.redpitaya.com/

 

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Visitor jarez95
Visitor
245 Views
Registered: ‎04-25-2019

Re: Block Design Flow & .SV top fle

Hey, thanks for the reply.

I have also made a post in their forum. If there is any details I can elaborate on, I will be happy to do so.
I posted in this forum as I was hoping to target my 2nd and 4th paragraph, about perhaps making a verilog wrapper interconnect for the sv file and to also gather opinions regarding transitioning to the Xilinx SDK ?

Best Regards, Jarez95