UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor chris.miller
Visitor
5,177 Views
Registered: ‎08-11-2015

Block Design adding interface to Custom IP pin

I've created several custom IP and packaged them and added them to a block design. One IP, I'll call it magicIP, has two clocks, clkA and clkB.  clkA is the clock for an AXI interface and for a master AXIS interface.  clkB has no AXI or AXIS interfaces assigned to it. When I package the magicIP I make sure that clkA and clkB are set up correctly.  I then add this IP to my block design, wire it up and validate the design. Validation passes, and I can generate a bit file.  But if I then go back and modify the block design, such as adding IP, changing wiring, updating other IP, my magicIP suddenly (magically) gets an interface associated with clkB.  This interface is the AXIS master, which is still also associated with clkA.  Now when I validate, I get a clock domain error between the AXIS master and slave clocks with the clkB being incorrectly being assigned to the magicIP's AXIS master port. If I delete magicIP from the block design and then add it again, then I pass validation again and can generate a bit file.  I see this interface appearing by viewing the Block Pin Properties of clkB.

Haven't been able to find any references to this problem.  Any ideas????

Vivado 2015.3, Windows 7

0 Kudos