Block Design with an IP having global defines

[teddywhy]

Dear Sir,

I am using Block Design but one of my IP has global defines. 

Do I need to have same global defines when using Block Design ?

Regards,

Teddy Wong.

[vsrunga]

Hi, 

Not exactly.

UG1118 says - After packaging Vivado tool treats global `include files as standard Verilog or Verilog Header files.
To package a design that uses global ‘include files, you must modify the HDL to place the
`include statement at the top of any Verilog source file that references content from another Verilog or Verilog header file.

[teddywhy]

To be exactly, this ip has different configurations according to different external defines.

It looks like external defines is needed in final block design, isn't it ?

[vsrunga]

Hi, 

Are you packaging  RTL(with defines) and using it as a custom IP long with other IPs whose configuration is based on those defines? 

If yes, as other IPs don't have knowledge about those defines you should have them included..

[teddywhy · Accepted solution]

I have solved this problem by adding external defines to block design and ip package. Thanks.