06-07-2020 11:25 PM
06-08-2020 02:16 AM
UG1118 says - After packaging Vivado tool treats global `include files as standard Verilog or Verilog Header files.
To package a design that uses global ‘include files, you must modify the HDL to place the
`include statement at the top of any Verilog source file that references content from another Verilog or Verilog header file.
06-08-2020 05:13 AM
To be exactly, this ip has different configurations according to different external defines.
It looks like external defines is needed in final block design, isn't it ?
06-08-2020 09:11 AM - edited 06-08-2020 09:31 AM
Are you packaging RTL(with defines) and using it as a custom IP long with other IPs whose configuration is based on those defines?
If yes, as other IPs don't have knowledge about those defines you should have them included..