10-09-2019 01:25 PM
10-11-2019 01:49 AM
The tool will use the range you set in the address editor tab to set the size of the memory. So just reduce the range corresponding to the BRAM in the address editor tab
10-11-2019 11:32 AM
It looks like depth fixed to 128K. I also tried to minimum range which is 4K from address editor but it shows 128K.
I've been using 2018.2 Vivado without a problem for this BRAM design, but I found this issue from 2019.1. The only difference is this tool version, and the target device which is UltraScale+ (xcvu9p-flgb2104). My previous project was with UltraScale.
Can you try 64-bit width BRAM with 32-bit BRAM controller (this is fixed for controller, correct?) from your side?
10-15-2019 02:39 AM
10-15-2019 12:04 PM
The issue has been resolved. In general, tool is not smart as human, so user needs some technique/sequence to generate/assign bit width for 512-bit width BRAM controller with Block Memory architecture from AXI4 interconnect in IP integrator, and successfully generated bit file having 256K of range from address editor per BRAM assigned to each of lane (total 8-lane) for JESD204C interface.