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208 Views
Registered: ‎04-12-2019

Block Memory Generator (8.4, Vivado 2019.1)

Hello, I got an error due to RAMB36/FIFO over-utilized during Vivado optimization stage. From AXI Interconnect, I am using 16-BRAM along with 16-AXI-BRAM-Controller, and each of BRAM has 64-bit width. "Memory Depth" from AXI BRAM Controller set 4096 automatically, and "Write Depth" from Block Memory Generator(8.4) set 131072 during Vivado optimization process. Initially, I set it as 4096 but the tool changed it to 131072. I think this causes FIFO over-utilization. Is there a way to fix this problem? Thanks, KW
AXI_BRAM_Controller_4p1.PNG
BRAM1.PNG
BRAM2.PNG
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Moderator
Moderator
155 Views
Registered: ‎11-09-2015

Re: Block Memory Generator (8.4, Vivado 2019.1)

HI knam@jariettech.com 

The tool will use the range you set in the address editor tab to set the size of the memory. So just reduce the range corresponding to the BRAM in the address editor tab


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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134 Views
Registered: ‎04-12-2019

Re: Block Memory Generator (8.4, Vivado 2019.1)

It looks like depth fixed to 128K. I also tried to minimum range which is 4K from address editor but it shows 128K.

I've been using 2018.2 Vivado without a problem for this BRAM design, but I found this issue from 2019.1. The only difference is this tool version, and the target device which is UltraScale+ (xcvu9p-flgb2104). My previous project was with UltraScale.

Can you try 64-bit width BRAM with 32-bit BRAM controller (this is fixed for controller, correct?) from your side?

Thanks,

KW

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Moderator
Moderator
99 Views
Registered: ‎11-09-2015

Re: Block Memory Generator (8.4, Vivado 2019.1)

HI knam@jariettech.com 

Can you share your project?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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83 Views
Registered: ‎04-12-2019

Re: Block Memory Generator (8.4, Vivado 2019.1)

Hi,

The issue has been resolved. In general, tool is not smart as human, so user needs some technique/sequence to generate/assign bit width for 512-bit width BRAM controller with Block Memory architecture from AXI4 interconnect in IP integrator, and successfully generated bit file having 256K of range from address editor per BRAM assigned to each of lane (total 8-lane) for JESD204C interface.

Thanks,

KW

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