cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
dpaul24
Scholar
Scholar
981 Views
Registered: ‎08-07-2014

Bus Interface property FREQ_HZ mismatch for a custom IP core and the Xilinx VTPG core

Jump to solution

Hello,

I am using Vivado 2018.1.

I have a block diagram where I am connecting the Xilinx VTPG IP core to a custom IP. This custom IP is nothing but a AXI4Lite master which configures the VTPG registers.

When I validate the block design I get the following error-

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_tpg_0/s_axi_CTRL(150000000) and /axi4lite_m_w_0/axi4lite_m(100000000)
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

After a few searches took me to this AR - https://www.xilinx.com/support/answers/56610.html

As it says for all AXI clock ports made external, the default FREQ_HZ  is 100M. Now the VTPG input clock is supposed to be 150M and due to this frequency mismatch I am getting the above error.

Now I am looking for a way to specify or correct this FREQ_HZ for my aclk_150M_i. How can I do that?

Because, under Properties --> Config, I do not get an option to edit the FREQ_HZ parameter. Or have I made a mistake during packaging my IP (in this case, please also suggest what needs to be corrected).

7.jpg

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

Tags (1)
0 Kudos
Reply
1 Solution

Accepted Solutions
dpaul24
Scholar
Scholar
654 Views
Registered: ‎08-07-2014

@vsrunga,

I now have a synth project. Well many things had to be changed.

I had to change my axi4lite master RTL to VHDL from VHDL2008, else using 2018.1 I was getting some error messages.

I re-read the UG and after some tries could generate a clean custom IP when I packaged the complete project. Initially I was using the Directory option to package my IP (while I think this option should also work, I did not try it for lack of time).

Finally in the BD of the target project (where the IP was added) I had to change the FREQ_HQ parameter of the axi4lite 'interface definition' which connects the axi4lite master and the TPG IP core (thanks to Drsaab for pointing this out, I should have read the error msgs more carefully).

Well I am still learning the intricacies of Vivado BD, by hand-instantiation I could have achieved this target within 30min, here playing around with DB cost me 5 hours!

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

View solution in original post

7 Replies
DrSAB
Observer
Observer
963 Views
Registered: ‎05-29-2020

(1) Delete the slck_150M_i port.
(2) Create a new port; select the type to be Clock and the Frequency(MHz) field will be enabled for you to set the frequency. 
(3) Connect this new port to the bd. 

Capture.PNG

 

 

 

 

dpaul24
Scholar
Scholar
944 Views
Registered: ‎08-07-2014

@DrSAB,

Thanks it works. But I still have the fundamental error message...

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_tpg_0/s_axi_CTRL(150000000) and /axi4lite_m_w_0/axi4lite_m(100000000)

TCL Output:

.
.
save_bd_design
Wrote  : <C:/xil_tutorials/my_projects/hdmi_pass_vtpg/hdmi_pass_vtpg.srcs/sources_1/bd/hdmi_pass_vtpg/hdmi_pass_vtpg.bd> 
Wrote  : <C:/xil_tutorials/my_projects/hdmi_pass_vtpg/hdmi_pass_vtpg.srcs/sources_1/bd/hdmi_pass_vtpg/ui/bd_cc0a773c.ui> 
validate_bd_design
CRITICAL WARNING: [BD 41-1356] Address block </v_tpg_0/s_axi_CTRL/Reg> is not mapped into </axi4lite_m_w_0/axi4lite_m>. Please use Address Editor to either map or exclude it.
CRITICAL WARNING: [BD 41-967] AXI interface pin /axi4lite_m_w_0/axi4lite_m is not associated to any clock pin. It may not work correctly.
CRITICAL WARNING: [BD 41-1356] Address block </v_tpg_0/s_axi_CTRL/Reg> is not mapped into </axi4lite_m_w_0/axi4lite_m>. Please use Address Editor to either map or exclude it.
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /v_tpg_0/s_axi_CTRL(150000000) and /axi4lite_m_w_0/axi4lite_m(100000000)
ERROR: [Common 17-39] 'validate_bd_design' failed due to earlier errors.

8.jpg

What about the Critical Warnings listed?

Is it related to the way I ma packaging the custom IP core?

------------

Basically I have this Warning when I created the IP package, while combining the AXI4Lite signals....

1.jpg

And there was no way I could associate a clock....As you see from the SS below, I didn't get any list from where I could associate a clock for my AXI4Lite interface.

2.jpg

 

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
Reply
DrSAB
Observer
Observer
918 Views
Registered: ‎05-29-2020

Go other way around. It is axi4lite_m which is set to 100MHz and not associated to a clock. 
(1) Disconnect the clks wires; delete the sclk_150m port. 
(2) Make axi4lite_m a port , set the type and clock frequency. 
(3) Connect the VTPG clock. 

This should help vivado resolve the FREQ_HZ property. 

0 Kudos
Reply
vsrunga
Xilinx Employee
Xilinx Employee
888 Views
Registered: ‎07-11-2011

Hi,

Do you have X_INTERFACE_INFO attribute in your vhd?  If not can you try adding it and see if Associate_Clocks shows options ? 

attribute X_INTERFACE_INFO of axi4lite_clk_i : Signal is "xilinx.com:signal:clock:1.0 axi4lite_clk_i CLK";

Other way is simply drag and drop your axi4lite_m_w.vhd on to bd and see if module referencing flow helps 

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
0 Kudos
Reply
dpaul24
Scholar
Scholar
688 Views
Registered: ‎08-07-2014

@DrSAB,

(2) Make axi4lite_m a port , set the type and clock frequency

Will try.Thanks

@vsrunga,

The X_INTERFACE_INFO didn't help. K got the same message.

Then I tried your other suggestion - Other way is simply drag and drop your axi4lite_m_w.vhd on to bd and see if module referencing flow helps

It works but keeps the axi4lite lite signals separated. I know I can connect them one by one and BD should pass validation. But that is not my intention, I want to keep the axi4lite signals as a group, keeping the clk and reset separate. How to achieve that?

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
Reply
vsrunga
Xilinx Employee
Xilinx Employee
675 Views
Registered: ‎07-11-2011

Hi, 

Can you crosscheck your RTL against "Inferring AXI Interfaces" from this UG ?

If that doesn't help please upload your axi4lite_m_w.vhd to take a look..

---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
dpaul24
Scholar
Scholar
655 Views
Registered: ‎08-07-2014

@vsrunga,

I now have a synth project. Well many things had to be changed.

I had to change my axi4lite master RTL to VHDL from VHDL2008, else using 2018.1 I was getting some error messages.

I re-read the UG and after some tries could generate a clean custom IP when I packaged the complete project. Initially I was using the Directory option to package my IP (while I think this option should also work, I did not try it for lack of time).

Finally in the BD of the target project (where the IP was added) I had to change the FREQ_HQ parameter of the axi4lite 'interface definition' which connects the axi4lite master and the TPG IP core (thanks to Drsaab for pointing this out, I should have read the error msgs more carefully).

Well I am still learning the intricacies of Vivado BD, by hand-instantiation I could have achieved this target within 30min, here playing around with DB cost me 5 hours!

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

View solution in original post