01-25-2013 02:34 PM
I've not managed to pass item #6 on page 25 of 150.
Every item is greyed out because the Device chosen in the tutorial isn't supported.
I've installed the ISE with WebPack licence on Windows.
Am I allowed to do this in WebPack mode?
I've searched through the Forum with a limited search string, but come up trumps.
01-28-2013 02:08 PM
01-25-2013 02:53 PM
Check that the version of webpack has the part you need to support.
It may be that you are using too new a version.
01-26-2013 07:30 PM
As long as you're not using "Vivado" webpack, it should support Spartan 3, however you
may not be able to support the largest parts (3S1000 or larger IIRC) using webpack. If you
don't see Spartan 3 at all, you may have loaded Vivado instead of ISE. Up until very
recently Vivado was not available as a webpack. I can never find the link to the software
support web page, but it shows exactly which devices are supported by each version
of the tools.
01-28-2013 02:08 PM
02-26-2013 05:03 AM
Sorry for the delay in getting back to you, howardp. Got sidetracked with another project
Your suggestion cracked the problem !
03-03-2013 11:37 AM
I've been trying to compile the UG695 tutorial for the Spartan 6 XC6slx16 FPGA.
This tutorialwas written for the Spartan 3.
Has anyone managed to do this successfully? I'm being challenged by the DCM clock generator. You have to manually create clocks with a raft of more settings. Yet when I think I've done it, I get an error during map stating the VCO frequency is beyond its limits.
Actually, my eval license has run out :(, So I'm reverting to a WebPack licence. WHen I looked at the product matrix, I am right in thinking the FPGA (I have on a digilent board) is covered by the WEBPACK licence?
03-04-2013 06:38 AM
Yes, the XC6SLX16 is covered by the WebPack license, but you don't get the EDK tools.
WebPack is essentially the "Logic Edition" with a restricted set of parts.
As for the DCM issues, I would suggest using the Core Generator's clocking wizard.
This allows you to enter the desired frequencies and phases and automatically
generates code that instantiates DCM's or PLL's as required to generate your
clocks. You can then edit the generated source, if it doesn't quite match your
interface requirements. But it does a good job of making sure that all of the
requirements of the DCM or PLL (like VCO frequency) are met.
03-04-2013 07:45 AM
I did actually manage to create the a successful DCM and clock generator....thing is...I'm not quite sure how.
I had problems generating a 26.2144MHz from a 50MHz input. Yet when I changed it to 26MHz output, it worked fine.
The complaint had to do with a VCO frequency out of bounds. I need to see how to trigger that fault again.