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Registered: ‎06-23-2014

Can I mix IP Integrator Block Diagram and custom RTL?

I'm using Vivado 2018.1

 

Perhaps @markcurry and @muzaffer who commented at https://forums.xilinx.com/t5/Welcome-Join/IP-Integrator-systemverilog-interface-support/m-p/685249/highlight/true#M34565 would like to comment...  Perhaps I just need to know the write search terms or a first base document.   [EDIT: Hmmm... ug898-vivado-embedded-design.pdf page 19 "Creating an HDL Wrapper" suggests the answer is yes, but doesn't address constraints.]

 

What I want to do is the following:

  1. I've built the Hello_World example from  the microblaze-quick-start-guide.pdf .
  2. It created base_mb_wrapper.vhd and I see in the Sources window that it's Set as Top.
  3. I want to push base_mb_wrapper.vhd down a level, add a bunch more logic and some new pins that I Make External
  4. Write a new Top_Module.sv that connects the base_mb_wrapper.vhd with MicroBlaze and other logic, to my own suite of custom RTL.
  5. Then update a constraints file I already have to get everything to the right FPGA pins.  Note that right now I have no clue how the base_mb_wrapper.vhd external connections are getting routed to pins.

Now,Ii'm pretty confident that I can do steps 1 through 4.  It should simply be a matter of connecting up the correct signals.  (Even when mixing VHDL and System Verilog, if you noticed that .vhd vs .sv subtlety.)

  • But will Vivado fight me in this?
  • And then there's the constraints and pin connections problem mentioned above.
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Registered: ‎06-23-2014

Re: Can I mix IP Integrator Block Diagram and custom RTL?

I'm trying to make this happen and of course run into trouble immediately.

 

[EDIT: PARTIALLY SOLVED.  This was a dumb error on my part.  My SystemVerilog call to base_mb_wrapper provided the comma separated parameters list, but failed to have the "." before each name.  This may have done ordered parameters rather than parameters by name, causing mis-connection of signals.  NEVERTHELESS, I'm still in the dark about pin constraints.  I got this working *without* adding my own.  I'll try to add my own, that have different signal names, and see what happens...]

 

After pushing base_mb_wrapper.vhd down a later, I created MFF_Top.sv to call/invoke it.  However, Implementation/Place gets an error: "[Place 30-378] Input pin of input buffer base_mb_wrapper/base_mb_i/clk_wiz_1/inst/clkin1_ibufgds has an illegal connection to a logic constant value."

 

I trace through the code and I'm pretty sure this is because my MFF_Top.sv has a signal "sys_diff_clock_clk_p" or "sys_diff_clock_clk_n" that is ***NOT*** being logically connected to the KC705 clock pins.  I suspect this is because there is no constraint specifying the pin connection.  So I'm back to constraints questions.  How did it work in base_mb_wrapper.hvd itself?  Is it the crazy case that inside the block diagram totally disjoint method of assigning pins applies, and that I must separately now go add a constraints file for these pins?  Some overview doc that DIRECTLY addresses where block diagram knows pin positions would help...

 

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Registered: ‎06-23-2014

Re: Can I mix IP Integrator Block Diagram and custom RTL?

Now I get the Place error

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33.  For example, the following two ports in this bank have conflicting VCCOs: GPIO_LED_0_LS (LVCMOS15, requiring VCCO=1.500) and SYSCLK_P (LVDS, requiring VCCO=1.800).

 

Now this appears to make sense at first.  But realize that I am using the EXACT same constraints file now as a previous project that was building successfully.  Both my new hybrid IP Integrator project and my old strictly RTL project had top modules using both GPIO_LED_0_LS and SYSCLK_P.  So how did the old project build (Vivado 2017.1) and the new project not (Vivado 2018.1)?

 

Excerpts from my explicit constraints file, which shows up in the Sources window under Constraints / constrs_1:

set_property DCI_CASCADE {32 34} [get_iobanks 33]
set_property PACKAGE_PIN AB8 [get_ports GPIO_LED_0_LS]
set_property IOSTANDARD LVCMOS15 [get_ports GPIO_LED_0_LS]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN AD12 [get_ports SYSCLK_P]

 

Meanwhile, note that KC705 schematic page 7 shows Bank 33 with  VCCO signals all conencted to VCC1V5_FPGA.  So it seems 1.5V is corrrect.  Why was SYSCLK_P working on my previous project if LVDS wants 1.8V?  How are any KC705 projects working if the schematic shows 1.5V being used?  (Is that programmable to 1.8V?  I follow it to schematic page 41, where it's hard to tell.)

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Registered: ‎06-23-2014

Re: Can I mix IP Integrator Block Diagram and custom RTL?

OK, I may be close to resolving this, but no all the way yet...  In neither project is DIFF_TERM set in the constraints file.  However, in the old project, the Top module invokes a IBUFGDS with parameter .DIFF_TERM("FALSE"). This made the old project work.

 

For the new project...  While false should be the default value of DIFF_TERM, it appears that the block diagram from the Hello_World example must be setting it to true.  I need to somehow override that from true to false. 

 

Setting DIFF_TERM to FALSE in my constraints file didn't help.  AGAIN I come to the question of where in the world are the constraints for the original IP Integrator block diagram?  

 

[EDIT: If I keep the majority of my old constraints in the new project, including the uart and led connections, but comment out simply the SYSCLK_P and SYSCLK_N, as well as make my new top module refer to the sys_diff_clock_clk_p|n names used by the IP Integrator, then the bitstream builds and works.  Definitely those sys_diff_clock_clk_p|n  are being somehow connected to AD12|AD11 (respectively), but I can't find it.  It's not in the <xilinx install folder>...<kc705> board file board.xml

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