10-22-2019 05:55 PM
I generated an image processing algorithm using a bunch of Xilinx IP. I have packaged the IP and then tried to reference the IP from a larger project that is pulling the image processing block as a component into custom RTL. The image processing block contains Concats, Constants, and Slices. Apparently, these blocks can not be included in custom RTL because I get the following error:
"Reference '<<customRtl>>' contains sub-design file '<<const/slice/etc>>.xci'. This sub-design is not allowed in the reference due to following reason(s): IP components that are IPI-only are not supported for module references."
Is there any work-around for this short of just writing the whole thing and instantiating the IP blocks that I want? As a point of note, I would have started this way in the first place, but was trying to give the block diagram a chance. It seems that Xilinx prefers that we use the block diagram. But if not all of the components I put on a block diagram can actually be reduced into IP that can be referenced in other places, this severely limits the block diagrams utility. Perhaps, I am approaching the problem incorrectly?
10-22-2019 07:05 PM
Hi email@example.com ,
I guess the concat or Slice IPs are not supported for IP inferencing, please cgeck page no.221 of below UG link on detailed information:
Also please check this post if that helps in resolving your issue:
10-23-2019 08:10 AM
Thanks for your response. I did verify that the Concat and Slice, at least, were not in the list of IP that support inferencing using the 'get_ipdefs -filter SUPPORTS_MODREF==1' command.
I had come across page 221 of UG994 prior to posting, but wasn't sure it exactly applied. It wasn't clear to me why Concat, Slice, or Constant would fall under any of the items listed. And since they seem to form a necessary part of a block diagram (especially when using the CORDIC which can have multiple parameters that must be concatenated into a single input vector), it seems strange that these would not be supported.
Interestingly, I did find this morning that despite the filmgmt error, I was able to get the design to compile and simulate (behaviorally). This took a little work. I had to manually change the compile order for a reason that would only complicate this thread. But, in any case, this error appears to be inconsequential. I haven't reviewed the results in enough detail to say whether the referenced IP is working correctly, but will report on that when I know.
It would be nice to understand why the error is showing up and what, if anything, could be done about it in the future when I have more time. Can you confirm that the problem is benign? To recreate it, you could, for example, build a simple block design that includes a CORDIC and two inputs that are concatenated together inside the diagram. Package this as IP and export. The try to instantiate that in an RTL module in another project. This is effectively what I am doing.
Perhaps I could use some more education. I had assumed that when I packaged IP, I could then use it anywhere, whether in a block diagram, or directly in RTL. Maybe I am approaching this incorrectly.