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10,860 Views
Registered: ‎11-03-2013

Cannot add fifo.ngc file to my top module

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Hey guys, when I add my fifo.ngc file to my top module it says it is added but it is shown under the unassigned user library modules tree. I need ngc file for my project to work in a proper manner. I did not face this problem using ISE13.2, but now when using ISE12.4 which I should, as stated by my boss I face this problem. Help out guys please!

 

Regards

jeevanreddymandali
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1 Solution

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Xilinx Employee
Xilinx Employee
16,227 Views
Registered: ‎07-11-2011

Re: Cannot add fifo.ngc file to my top module

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Hi,

 

What is the purpose that you have brought FIFO_gen_7.2.ngc  in this project instead of genearting the core and instantiating the .vho?

What is your ISE version ? do you wanted to use old FIFO core and hence preferred this approcah?

If 7.2 FIFO is generated with your existing ISE and if you know where to interface the FIFO in your project (write and read clocks, enables) add .xco and use .vho file to declare the component and insantiate the FIFO.

 

Hope this helps

 

Regards,

Vanitha.

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7 Replies
Xilinx Employee
Xilinx Employee
10,845 Views
Registered: ‎07-11-2011

Re: Cannot add fifo.ngc file to my top module

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Hi,

 

You mean to say your .ngc is not shown in proper hierarchy?

If yes have you instantiated the .ngc with correct name in  wrapper?

 

Can you show snapshots of hierarchy and warpper file?

 

 

Regards,

Vanitha.

---------------------------------------------------------------------------------------------
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Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
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Registered: ‎11-03-2013

Re: Cannot add fifo.ngc file to my top module

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hierarchy.png

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity XOY3_4lane_GTX_WRAPPER is
generic
(
    SIM_MODE                : string    := "FAST"; -- Set to Fast Functional Simulation Model

    --Simulation attributes
    CHAN_BOND_LEVEL_0 : integer := 0;
    CHAN_BOND_LEVEL_1 : integer := 0;

    SIM_GTXRESET_SPEEDUP :integer :=   0;      --Set to 1 to speed up sim reset
    SIM_PLL_PERDIV2      :bit_vector  :=   x"0a0";    --Set to the VCO Unit Interval time
    --Channel bond MASTER/SLAVE connection
    CHAN_BOND_MODE_0 :string := "SLAVE";
    --Channel bond MASTER/SLAVE connection
    CHAN_BOND_MODE_0_LANE1 :string := "MASTER";
    --Channel bond MASTER/SLAVE connection
    CHAN_BOND_MODE_0_LANE2 :string := "SLAVE";
    --Channel bond MASTER/SLAVE connection
    CHAN_BOND_MODE_0_LANE3 :string := "SLAVE";
    
    CHAN_BOND_MODE_1 :string := "SLAVE";
    CHAN_BOND_MODE_1_LANE1 :string := "MASTER";
    CHAN_BOND_MODE_1_LANE2 :string := "SLAVE";
    CHAN_BOND_MODE_1_LANE3 :string := "SLAVE";
    --Refclk attributes
    CLKINDC_B            :boolean :=   TRUE 
);
port
(
---------------------- Loopback and Powerdown Ports ----------------------
LOOPBACK_IN                               : in    std_logic_vector (2 downto 0);
--------------------- Receive Ports - 8b10b Decoder ----------------------

RXCHARISCOMMA_OUT_1 : out   std_logic_vector (1 downto 0); 
RXCHARISCOMMA_OUT_2 : out   std_logic_vector (1 downto 0); 
RXCHARISCOMMA_OUT_3 : out   std_logic_vector (1 downto 0); 
RXCHARISCOMMA_OUT_4 : out   std_logic_vector (1 downto 0); 

RXCHARISK_OUT_1     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_2     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_3     : out   std_logic_vector (1 downto 0);
RXCHARISK_OUT_4     : out   std_logic_vector (1 downto 0);

RXDISPERR_OUT_1     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_2     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_3     : out   std_logic_vector (1 downto 0);
RXDISPERR_OUT_4     : out   std_logic_vector (1 downto 0);

RXNOTINTABLE_OUT_1  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_2  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_3  : out   std_logic_vector (1 downto 0);
RXNOTINTABLE_OUT_4  : out   std_logic_vector (1 downto 0);
----------------- Receive Ports - Channel Bonding Ports -----------------

ENCHANSYNC_IN_1     : in    std_logic;
ENCHANSYNC_IN_2     : in    std_logic;
ENCHANSYNC_IN_3     : in    std_logic;
ENCHANSYNC_IN_4     : in    std_logic;

CHBONDDONE_OUT_1    : out   std_logic;
CHBONDDONE_OUT_2    : out   std_logic;
CHBONDDONE_OUT_3    : out   std_logic;
CHBONDDONE_OUT_4    : out   std_logic;

----------------- Receive Ports - Clock Correction Ports -----------------

RXBUFERR_OUT_1      : out   std_logic;
RXBUFERR_OUT_2      : out   std_logic;
RXBUFERR_OUT_3      : out   std_logic;
RXBUFERR_OUT_4      : out   std_logic;

------------- Receive Ports - Comma Detection and Alignment --------------

RXREALIGN_OUT_1     : out   std_logic;
RXREALIGN_OUT_2     : out   std_logic;
RXREALIGN_OUT_3     : out   std_logic;
RXREALIGN_OUT_4     : out   std_logic;

ENMCOMMAALIGN_IN_1  : in    std_logic;
ENMCOMMAALIGN_IN_2  : in    std_logic;
ENMCOMMAALIGN_IN_3  : in    std_logic;
ENMCOMMAALIGN_IN_4  : in    std_logic;

ENPCOMMAALIGN_IN_1  : in    std_logic;
ENPCOMMAALIGN_IN_2  : in    std_logic;
ENPCOMMAALIGN_IN_3  : in    std_logic;
ENPCOMMAALIGN_IN_4  : in    std_logic;

----------------- Receive Ports - RX Data Path interface -----------------
RXDATA_OUT_1        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_2        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_3        : out   std_logic_vector (15 downto 0);
RXDATA_OUT_4        : out   std_logic_vector (15 downto 0);

RXRECCLK1_OUT_1     : out   std_logic;
RXRECCLK1_OUT_2     : out   std_logic;
RXRECCLK1_OUT_3     : out   std_logic;
RXRECCLK1_OUT_4     : out   std_logic;

RXRECCLK2_OUT_1     : out   std_logic;
RXRECCLK2_OUT_2     : out   std_logic;
RXRECCLK2_OUT_3     : out   std_logic;
RXRECCLK2_OUT_4     : out   std_logic;

RXRESET_IN_1        : in    std_logic;
RXRESET_IN_2        : in    std_logic;
RXRESET_IN_3        : in    std_logic;
RXRESET_IN_4        : in    std_logic;
RXUSRCLK_IN                               : in    std_logic;
RXUSRCLK2_IN                              : in    std_logic;
----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------

RX1N_IN_1           : in    std_logic;
RX1N_IN_2           : in    std_logic;
RX1N_IN_3           : in    std_logic;
RX1N_IN_4           : in    std_logic;

RX1P_IN_1           : in    std_logic;
RX1P_IN_2           : in    std_logic;
RX1P_IN_3           : in    std_logic;
RX1P_IN_4           : in    std_logic;

--------------- Receive Ports - RX Polarity Control Ports ----------------
RXPOLARITY_IN_1     : in    std_logic;
RXPOLARITY_IN_2     : in    std_logic;
RXPOLARITY_IN_3     : in    std_logic;
RXPOLARITY_IN_4     : in    std_logic;

------------------- Shared Ports - Tile and PLL Ports --------------------

REFCLK                                    : in    std_logic;

GTXRESET_IN                               : in    std_logic;

PLLLKDET_OUT_1      : out   std_logic;
PLLLKDET_OUT_2      : out   std_logic;

REFCLKOUT_OUT_1     : out   std_logic;
REFCLKOUT_OUT_2     : out   std_logic;

-------------- Transmit Ports - 8b10b Encoder Control Ports --------------

TXCHARISK_IN_1      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_2      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_3      : in    std_logic_vector (1 downto 0);
TXCHARISK_IN_4      : in    std_logic_vector (1 downto 0);

---------------- Transmit Ports - TX Data Path interface -----------------

TXDATA_IN_1         : in    std_logic_vector (15 downto 0);
TXDATA_IN_2         : in    std_logic_vector (15 downto 0);
TXDATA_IN_3         : in    std_logic_vector (15 downto 0);
TXDATA_IN_4         : in    std_logic_vector (15 downto 0);

TXOUTCLK1_OUT_1     : out   std_logic;
TXOUTCLK1_OUT_2     : out   std_logic;
TXOUTCLK1_OUT_3     : out   std_logic;
TXOUTCLK1_OUT_4     : out   std_logic;

TXOUTCLK2_OUT_1     : out   std_logic;
TXOUTCLK2_OUT_2     : out   std_logic;
TXOUTCLK2_OUT_3     : out   std_logic;
TXOUTCLK2_OUT_4     : out   std_logic;

TXRESET_IN_1        : in    std_logic;
TXRESET_IN_2        : in    std_logic;
TXRESET_IN_3        : in    std_logic;
TXRESET_IN_4        : in    std_logic;
 
TXUSRCLK_IN                               : in    std_logic;       
TXUSRCLK2_IN                              : in    std_logic;

TXBUFERR_OUT_1      : out   std_logic;
TXBUFERR_OUT_2      : out   std_logic;
TXBUFERR_OUT_3      : out   std_logic;
TXBUFERR_OUT_4      : out   std_logic;

------------- Transmit Ports - TX Driver and OOB signalling --------------

TX1N_OUT_1          : out   std_logic;
TX1N_OUT_2          : out   std_logic;
TX1N_OUT_3          : out   std_logic;
TX1N_OUT_4          : out   std_logic;
TX1P_OUT_1          : out   std_logic;
TX1P_OUT_2          : out   std_logic;
TX1P_OUT_3          : out   std_logic;
TX1P_OUT_4          : out   std_logic;

POWERDOWN_IN                                       : in    std_logic                

);
end XOY3_4lane_GTX_WRAPPER;

architecture BEHAVIORAL of XOY3_4lane_GTX_WRAPPER is
  attribute core_generation_info               : string;
  attribute core_generation_info of BEHAVIORAL : architecture is "XOY3_4lane,aurora_8b10b_v6_1,{user_interface=AXI_4_Streaming, backchannel_mode=Sidebands, c_aurora_lanes=1, c_column_used=left, c_gt_clock_1=GTXD3, c_gt_clock_2=None, c_gt_loc_1=X, c_gt_loc_10=X, c_gt_loc_11=X, c_gt_loc_12=X, c_gt_loc_13=X, c_gt_loc_14=X, c_gt_loc_15=X, c_gt_loc_16=X, c_gt_loc_17=X, c_gt_loc_18=X, c_gt_loc_19=X, c_gt_loc_2=X, c_gt_loc_20=X, c_gt_loc_21=X, c_gt_loc_22=X, c_gt_loc_23=X, c_gt_loc_24=X, c_gt_loc_25=X, c_gt_loc_26=X, c_gt_loc_27=X, c_gt_loc_28=X, c_gt_loc_29=X, c_gt_loc_3=X, c_gt_loc_30=X, c_gt_loc_31=X, c_gt_loc_32=X, c_gt_loc_33=X, c_gt_loc_34=X, c_gt_loc_35=X, c_gt_loc_36=X, c_gt_loc_37=X, c_gt_loc_38=X, c_gt_loc_39=X, c_gt_loc_4=X, c_gt_loc_40=X, c_gt_loc_41=X, c_gt_loc_42=X, c_gt_loc_43=X, c_gt_loc_44=X, c_gt_loc_45=X, c_gt_loc_46=X, c_gt_loc_47=X, c_gt_loc_48=X, c_gt_loc_5=X, c_gt_loc_6=X, c_gt_loc_7=1, c_gt_loc_8=X, c_gt_loc_9=X, c_lane_width=2, c_line_rate=3.125, c_nfc=false, c_nfc_mode=IMM, c_refclk_frequency=156.25, c_simplex=false, c_simplex_mode=TX, c_stream=false, c_ufc=false, flow_mode=None, interface_mode=Framing, dataflow_config=Duplex}";
--***************************** Compopnent Declaration ****************************
component XOY3_4lane_GTX_TILE is
generic
(
  -- Simulation attributes
    TILE_SIM_MODE                : string    := "FAST"; -- Set to Fast Functional Simulation Model
    TILE_SIM_GTXRESET_SPEEDUP    : integer   := 0; -- Set to 1 to speed up sim reset
    TILE_SIM_PLL_PERDIV2         : bit_vector:= x"140"; -- Set to the VCO Unit Interval time 

    -- Channel bonding attributes
    TILE_CHAN_BOND_LEVEL_0       : integer   := 0;     -- 0 to 7. See UG for details
    TILE_CHAN_BOND_LEVEL_1       : integer   := 0;      -- 0 to 7. See UG for details
    
    TILE_CHAN_BOND_MODE_0        : string    := "OFF";  -- "MASTER", "SLAVE", or "OFF"
    TILE_CHAN_BOND_MODE_1        : string    := "OFF"  -- "MASTER", "SLAVE", or "OFF"
);
port 
(
   ------------------------ Loopback and Powerdown Ports ----------------------
    LOOPBACK0_IN                            : in   std_logic_vector(2 downto 0);
    LOOPBACK1_IN                            : in   std_logic_vector(2 downto 0);
    ----------------------- Receive Ports - 8b10b Decoder ----------------------
    RXCHARISCOMMA0_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXCHARISCOMMA1_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXCHARISK0_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXCHARISK1_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXDISPERR0_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXDISPERR1_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXNOTINTABLE0_OUT 		     	    : out std_logic_vector(1 downto 0);
    RXNOTINTABLE1_OUT 		     	    : out std_logic_vector(1 downto 0);
    ------------------- Receive Ports - Channel Bonding Ports ------------------
    RXCHANBONDSEQ0_OUT			    : out std_logic;
    RXCHANBONDSEQ1_OUT			    : out std_logic;
    RXCHBONDI0_IN			    : in std_logic_vector(3 downto 0);
    RXCHBONDI1_IN			    : in std_logic_vector(3 downto 0);
    RXCHBONDO0_OUT			    : out std_logic_vector(3 downto 0);
    RXCHBONDO1_OUT			    : out std_logic_vector(3 downto 0);
    RXENCHANSYNC0_IN			    : in std_logic;
    RXENCHANSYNC1_IN			    : in std_logic;
    ------------------- Receive Ports - Clock Correction Ports--
    RXCLKCORCNT0_OUT			    : out std_logic_vector(2 downto 0);
    RXCLKCORCNT1_OUT			    : out std_logic_vector(2 downto 0);
    --------------- Receive Ports - Comma Detection and Alignment --------------
    RXBYTEREALIGN0_OUT			    : out std_logic;
    RXBYTEREALIGN1_OUT			    : out std_logic;
    RXENMCOMMAALIGN0_IN			    : in std_logic;
    RXENMCOMMAALIGN1_IN			    : in std_logic;
    RXENPCOMMAALIGN0_IN			    : in std_logic;
    RXENPCOMMAALIGN1_IN			    : in std_logic;
    ------------------- Receive Ports - RX Data Path interface -----------------
    RXDATA0_OUT                             : out  std_logic_vector(15 downto 0);
    RXDATA1_OUT                             : out  std_logic_vector(15 downto 0);
    RXRESET0_IN                             : in   std_logic;
    RXRESET1_IN                             : in   std_logic;
    RXUSRCLK0_IN                            : in   std_logic;
    RXUSRCLK1_IN                            : in   std_logic;
    RXUSRCLK20_IN                           : in   std_logic;
    RXUSRCLK21_IN                           : in   std_logic;
    ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
    RXCDRRESET0_IN                          : in   std_logic;
    RXCDRRESET1_IN                          : in   std_logic;
    RXN0_IN                                 : in   std_logic;
    RXN1_IN                                 : in   std_logic;
    RXP0_IN                                 : in   std_logic;
    RXP1_IN                                 : in   std_logic;
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    RXBUFRESET0_IN                          : in   std_logic;
    RXBUFRESET1_IN                          : in   std_logic;
    RXBUFSTATUS0_OUT                        : out  std_logic_vector(2 downto 0);
    RXBUFSTATUS1_OUT                        : out  std_logic_vector(2 downto 0);
    TXBUFSTATUS0_OUT                        : out  std_logic_vector(1 downto 0);
    TXBUFSTATUS1_OUT                        : out  std_logic_vector(1 downto 0);
    -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
    RXCHANISALIGNED0_OUT			    : out std_logic;
    RXCHANISALIGNED1_OUT			    : out std_logic;
    RXCHANREALIGN0_OUT			    : out std_logic;
    RXCHANREALIGN1_OUT			    : out std_logic;
    ----------------- Receive Ports - RX Polarity Control Ports ----------------
    RXPOLARITY0_IN                          : in   std_logic;
    RXPOLARITY1_IN                          : in   std_logic;
    --------------------- Shared Ports - Tile and PLL Ports --------------------
    CLKIN_IN                                : in   std_logic;
    GTXRESET_IN                             : in   std_logic;
    PLLLKDET_OUT                            : out  std_logic;
    REFCLKOUT_OUT_1                           : out  std_logic;
    RESETDONE0_OUT                          : out  std_logic;
    RESETDONE1_OUT                          : out  std_logic;
    ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
    TXCHARISK0_IN			    : in std_logic_vector(1 downto 0);
    TXCHARISK1_IN			    : in std_logic_vector(1 downto 0);
    -------------- Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
    TXDATA0_IN                              : in   std_logic_vector(15 downto 0);
    TXDATA1_IN                              : in   std_logic_vector(15 downto 0);
    TXOUTCLK0_OUT                           : out  std_logic;
    TXOUTCLK1_OUT                           : out  std_logic;
    TXRESET0_IN                             : in   std_logic;
    TXRESET1_IN                             : in   std_logic;
    TXUSRCLK0_IN                            : in   std_logic;
    TXUSRCLK1_IN                            : in   std_logic;
    TXUSRCLK20_IN                           : in   std_logic;
    TXUSRCLK21_IN                           : in   std_logic;
    --------------- Transmit Ports - TX Driver and OOB signalling --------------
    TXN0_OUT                                : out  std_logic;
    TXN1_OUT                                : out  std_logic;
    TXP0_OUT                                : out  std_logic;
    TXP1_OUT                                : out  std_logic
	 
);
end component;

   signal tied_to_ground_i                                : std_logic;
   signal tied_to_ground_vec_i                            : std_logic_vector (63 downto 0);
   signal tied_to_vcc_i                                   : std_logic;
   signal chbondi                 : std_logic_vector (3 downto 0);
   signal combusin                : std_logic_vector (15 downto 0);
   signal chbondo                 : std_logic_vector (3 downto 0);
   signal combusout               : std_logic_vector (15 downto 0);
   signal open_rxbufstatus        : std_logic_vector (1 downto 0);
   signal open_txbufstatus        : std_logic;
   signal chbondi_LANE1                 : std_logic_vector (3 downto 0);
   signal combusin_LANE1                : std_logic_vector (15 downto 0);
   signal chbondo_LANE1                 : std_logic_vector (3 downto 0);
   signal combusout_LANE1               : std_logic_vector (15 downto 0);
   signal open_rxbufstatus_lane1        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_lane1        : std_logic;
   signal chbondi_LANE2                 : std_logic_vector (3 downto 0);
   signal combusin_LANE2                : std_logic_vector (15 downto 0);
   signal chbondo_LANE2                 : std_logic_vector (3 downto 0);
   signal combusout_LANE2               : std_logic_vector (15 downto 0);
   signal open_rxbufstatus_lane2        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_lane2        : std_logic;
   signal chbondi_LANE3                 : std_logic_vector (3 downto 0);
   signal combusin_LANE3                : std_logic_vector (15 downto 0);
   signal chbondo_LANE3                 : std_logic_vector (3 downto 0);
   signal combusout_LANE3               : std_logic_vector (15 downto 0);
   signal open_rxbufstatus_lane3        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_lane3        : std_logic;
   signal chbondi_LANE4                 : std_logic_vector (3 downto 0);
   signal combusin_LANE4                : std_logic_vector (15 downto 0);
   signal chbondo_LANE4                 : std_logic_vector (3 downto 0);
   signal combusout_LANE4               : std_logic_vector (15 downto 0);
   signal open_rxbufstatus_lane4        : std_logic_vector (1 downto 0);
   signal open_txbufstatus_lane4        : std_logic;
   signal chbondi_unused_i                                    : std_logic_vector (3 downto 0);
   signal combus_unused_i                                     : std_logic_vector (15 downto 0);
   --signal to output lock signal
   signal plllkdet_i                                      : std_logic;
   signal plllkdet_lane1_i                                      : std_logic;
   
   signal  rxelecidle0_i           : std_logic; 
   signal  rxelecidle1_i           : std_logic; 
   signal  resetdone0_i            : std_logic;
   signal  resetdone1_i            : std_logic;
   signal  rxelecidle0_lane1_i           : std_logic; 
   signal  rxelecidle1_lane1_i           : std_logic; 
   signal  resetdone0_lane1_i            : std_logic;
   signal  resetdone1_lane1_i            : std_logic;


begin

   tied_to_ground_i <= '0';
   tied_to_ground_vec_i(63 downto 0) <= x"0000000000000000";
   tied_to_vcc_i <= '1';

   chbondi_unused_i  <= "0000";
   combus_unused_i   <= X"0000";
--Assign lock signals
  PLLLKDET_OUT_1  <=   plllkdet_i;
  PLLLKDET_OUT_2  <=   plllkdet_lane1_i;

 
   --Connect channel bonding bus
   chbondi <= chbondo_LANE1;
 
   --Connect channel bonding bus
   chbondi_LANE1 <= chbondi_unused_i;
 
   --Connect channel bonding bus
   chbondi_LANE2 <= chbondo_LANE1;
 
   --Connect channel bonding bus
   chbondi_LANE3 <= chbondo_LANE2;

    
--*************************************************************************************************    
-------------------------------------EVEN GTX-----------------------------------------------
--*************************************************************************************************
   GTX_TILE_INST : XOY3_4lane_GTX_TILE 
   generic map
   (
          --_______________________ Simulation-Only Attributes __________________
           TILE_SIM_MODE                    => SIM_MODE, 
          TILE_SIM_GTXRESET_SPEEDUP    => SIM_GTXRESET_SPEEDUP,
          TILE_SIM_PLL_PERDIV2             => SIM_PLL_PERDIV2,
          TILE_CHAN_BOND_LEVEL_0           => 1,
          TILE_CHAN_BOND_LEVEL_1           => 2,
         TILE_CHAN_BOND_MODE_0            => CHAN_BOND_MODE_0,
 
          TILE_CHAN_BOND_MODE_1           =>  CHAN_BOND_MODE_1_LANE1
         ) 
port map (
         ------------------------ Loopback and Powerdown Ports ----------------------
          LOOPBACK0_IN                  => LOOPBACK_IN,
          LOOPBACK1_IN                  => LOOPBACK_IN,
         ----------------------- Receive Ports - 8b10b Decoder ----------------------
          RXCHARISCOMMA0_OUT             => RXCHARISCOMMA_OUT_2 ,
          RXCHARISCOMMA1_OUT             => RXCHARISCOMMA_OUT_1,
          RXCHARISK0_OUT                 => RXCHARISK_OUT_2,
          RXCHARISK1_OUT                 => RXCHARISK_OUT_1,
          RXDISPERR0_OUT             => RXDISPERR_OUT_2,
          RXDISPERR1_OUT             => RXDISPERR_OUT_1,
          RXNOTINTABLE0_OUT          => RXNOTINTABLE_OUT_2,
          RXNOTINTABLE1_OUT          => RXNOTINTABLE_OUT_1,
         ------------------- Receive Ports - Channel Bonding Ports ------------------
          RXCHANBONDSEQ0_OUT             => open,
          RXCHANBONDSEQ1_OUT             => open,
 
          RXCHBONDI0_IN                 => chbondi,
          RXCHBONDI1_IN                 => chbondi_LANE1,
          RXCHBONDO0_OUT                 => chbondo,
          RXCHBONDO1_OUT                 => chbondo_LANE1,
          RXENCHANSYNC0_IN              => ENCHANSYNC_IN_1,
          RXENCHANSYNC1_IN              => ENCHANSYNC_IN_2,
         ------------------- Receive Ports - Clock Correction Ports -----------------
          RXCLKCORCNT0_OUT               => open,
          RXCLKCORCNT1_OUT               => open,
         --------------- Receive Ports - Comma Detection and Alignment --------------
          RXBYTEREALIGN0_OUT             => RXREALIGN_OUT_2 ,
          RXBYTEREALIGN1_OUT             => RXREALIGN_OUT_1 ,
          RXENMCOMMAALIGN0_IN           => ENMCOMMAALIGN_IN_2,
          RXENMCOMMAALIGN1_IN           => ENMCOMMAALIGN_IN_1,
          RXENPCOMMAALIGN0_IN           => ENPCOMMAALIGN_IN_2,
          RXENPCOMMAALIGN1_IN           => ENPCOMMAALIGN_IN_1,
         ------------------- Receive Ports - RX Data Path interface -----------------
 
          RXDATA0_OUT                   => RXDATA_OUT_2,
          RXDATA1_OUT                   => RXDATA_OUT_1,
          RXRESET0_IN                   => RXRESET_IN_2 ,
          RXRESET1_IN                   => RXRESET_IN_1,
          RXUSRCLK0_IN                  => RXUSRCLK_IN,
          RXUSRCLK1_IN                  => RXUSRCLK_IN ,
          RXUSRCLK20_IN                 => RXUSRCLK2_IN,
          RXUSRCLK21_IN                 => RXUSRCLK2_IN,
         ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
             
          RXCDRRESET0_IN                => tied_to_ground_i,
          RXCDRRESET1_IN                => tied_to_ground_i,
          RXN0_IN                       => RX1N_IN_2,
          RXN1_IN                       => RX1N_IN_1,
          RXP0_IN                       => RX1P_IN_2,
          RXP1_IN                       => RX1P_IN_1,
             
         -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
          RXBUFRESET0_IN                => tied_to_ground_i,
          RXBUFRESET1_IN                => tied_to_ground_i,

          RXBUFSTATUS0_OUT(2)            => RXBUFERR_OUT_2 ,
          RXBUFSTATUS0_OUT(1 downto 0)   => open_rxbufstatus_lane1(1 downto 0),

          RXBUFSTATUS1_OUT(2)            => RXBUFERR_OUT_1,
          RXBUFSTATUS1_OUT(1 downto 0)   => open_rxbufstatus(1 downto 0),

          TXBUFSTATUS0_OUT(1)            => TXBUFERR_OUT_2 ,
          TXBUFSTATUS0_OUT(0)            => open_txbufstatus_lane1,
                                                                                                                                                            
          TXBUFSTATUS1_OUT(1)            => TXBUFERR_OUT_1,
          TXBUFSTATUS1_OUT(0)            => open_txbufstatus,
                     
          RXCHANISALIGNED0_OUT           => CHBONDDONE_OUT_2,
          RXCHANISALIGNED1_OUT           => CHBONDDONE_OUT_1,
          RXCHANREALIGN0_OUT             => open,
          RXCHANREALIGN1_OUT             => open,

         ----------------- Receive Ports - RX Polarity Control Ports ----------------
          RXPOLARITY0_IN                => RXPOLARITY_IN_2,
          RXPOLARITY1_IN                => RXPOLARITY_IN_1,
        --------------------- Shared Ports - Tile and PLL Ports --------------------
          CLKIN_IN                      => REFCLK,

          GTXRESET_IN                   => GTXRESET_IN,
          PLLLKDET_OUT                   => plllkdet_i,
          REFCLKOUT_OUT_1                  => REFCLKOUT_OUT_1,
          RESETDONE0_OUT                 => resetdone0_i,
          RESETDONE1_OUT                 => resetdone1_i,
          
          ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
          TXCHARISK0_IN     => TXCHARISK_IN_2,
          TXCHARISK1_IN     => TXCHARISK_IN_1,
          ------------------ Transmit Ports - TX Data Path interface -----------------
          TXDATA0_IN                 => TXDATA_IN_2,
          TXDATA1_IN                 => TXDATA_IN_1,
          TXOUTCLK0_OUT                  => TXOUTCLK1_OUT_2,
          TXOUTCLK1_OUT                  => TXOUTCLK1_OUT_1,
          TXRESET0_IN                   => TXRESET_IN_2 ,
          TXRESET1_IN                   => TXRESET_IN_1,
          TXUSRCLK0_IN                  => TXUSRCLK_IN,
          TXUSRCLK1_IN                  => TXUSRCLK_IN,
          TXUSRCLK20_IN                 => TXUSRCLK2_IN,
          TXUSRCLK21_IN                 => TXUSRCLK2_IN,
          --------------- Transmit Ports - TX Driver and OOB signalling --------------
          TXN0_OUT                       => TX1N_OUT_2,
          TXN1_OUT                       => TX1N_OUT_1,
          TXP0_OUT                       => TX1P_OUT_2,
          TXP1_OUT                       => TX1P_OUT_1
);

GTX_TILE_INST_LANE1 : XOY3_4lane_GTX_TILE  
 
   generic map
   (
          --_______________________ Simulation-Only Attributes __________________
          TILE_SIM_MODE                    => SIM_MODE, 
          TILE_SIM_GTXRESET_SPEEDUP    => SIM_GTXRESET_SPEEDUP,
          TILE_SIM_PLL_PERDIV2             => SIM_PLL_PERDIV2,
          TILE_CHAN_BOND_LEVEL_0           => 1,
          TILE_CHAN_BOND_LEVEL_1           => 0,
 
          TILE_CHAN_BOND_MODE_0           => CHAN_BOND_MODE_0_LANE2,
          TILE_CHAN_BOND_MODE_1           =>  CHAN_BOND_MODE_1_LANE3
         ) 
port map (
--*************************************************************************************************            
-------------------------------------Both GTXs in a Tile-------------------------------------------
--*************************************************************************************************
         ------------------------ Loopback and Powerdown Ports ----------------------
          LOOPBACK0_IN                  => LOOPBACK_IN,
          LOOPBACK1_IN                  => LOOPBACK_IN,
         ----------------------- Receive Ports - 8b10b Decoder ----------------------
          RXCHARISCOMMA0_OUT             => RXCHARISCOMMA_OUT_3 ,
          RXCHARISCOMMA1_OUT             => RXCHARISCOMMA_OUT_4,
          RXCHARISK0_OUT                 => RXCHARISK_OUT_3,
          RXCHARISK1_OUT                 => RXCHARISK_OUT_4,
          RXDISPERR0_OUT             => RXDISPERR_OUT_3,
          RXDISPERR1_OUT             => RXDISPERR_OUT_4,
          RXNOTINTABLE0_OUT          => RXNOTINTABLE_OUT_3,
          RXNOTINTABLE1_OUT          => RXNOTINTABLE_OUT_4,
         ------------------- Receive Ports - Channel Bonding Ports ------------------
          RXCHANBONDSEQ0_OUT             => open,
          RXCHANBONDSEQ1_OUT             => open,
          RXCHBONDI0_IN                 => chbondi_LANE2,
          RXCHBONDI1_IN                 => chbondi_LANE3,
          RXCHBONDO0_OUT                => chbondo_LANE2,
          RXCHBONDO1_OUT                => chbondo_LANE3,
          RXENCHANSYNC0_IN              => ENCHANSYNC_IN_3,
          RXENCHANSYNC1_IN              => ENCHANSYNC_IN_4,
         ------------------- Receive Ports - Clock Correction Ports -----------------
          RXCLKCORCNT0_OUT               => open,
          RXCLKCORCNT1_OUT               => open,
         --------------- Receive Ports - Comma Detection and Alignment --------------
          RXBYTEREALIGN0_OUT             => RXREALIGN_OUT_3 ,
          RXBYTEREALIGN1_OUT             => RXREALIGN_OUT_4 ,
          RXENMCOMMAALIGN0_IN           => ENMCOMMAALIGN_IN_3,
          RXENMCOMMAALIGN1_IN           => ENMCOMMAALIGN_IN_4,
          RXENPCOMMAALIGN0_IN           => ENPCOMMAALIGN_IN_3,
          RXENPCOMMAALIGN1_IN           => ENPCOMMAALIGN_IN_4,
         ------------------- Receive Ports - RX Data Path interface -----------------
 
          RXDATA0_OUT                   => RXDATA_OUT_3,
          RXDATA1_OUT                   => RXDATA_OUT_4,
          RXRESET0_IN                   => RXRESET_IN_3 ,
          RXRESET1_IN                   => RXRESET_IN_4,
          RXUSRCLK0_IN                  => RXUSRCLK_IN,
          RXUSRCLK1_IN                  => RXUSRCLK_IN ,
          RXUSRCLK20_IN                 => RXUSRCLK2_IN,
          RXUSRCLK21_IN                 => RXUSRCLK2_IN,
         ------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
             
          RXCDRRESET0_IN                => tied_to_ground_i,
          RXCDRRESET1_IN                => tied_to_ground_i,
          RXN0_IN                       => RX1N_IN_3,
          RXN1_IN                       => RX1N_IN_4,
          RXP0_IN                       => RX1P_IN_3,
          RXP1_IN                       => RX1P_IN_4,
             
         -------- Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
          RXBUFRESET0_IN                => tied_to_ground_i,
          RXBUFRESET1_IN                => tied_to_ground_i,

          RXBUFSTATUS0_OUT(2)            => RXBUFERR_OUT_3 ,
          RXBUFSTATUS0_OUT(1 downto 0)   => open_rxbufstatus_lane2(1 downto 0),

          RXBUFSTATUS1_OUT(2)            => RXBUFERR_OUT_4,
          RXBUFSTATUS1_OUT(1 downto 0)   => open_rxbufstatus_lane3(1 downto 0),

          TXBUFSTATUS0_OUT(1)            => TXBUFERR_OUT_3 ,
          TXBUFSTATUS0_OUT(0)            => open_txbufstatus_lane2,
                                                                                                                                                            
          TXBUFSTATUS1_OUT(1)            => TXBUFERR_OUT_4,
          TXBUFSTATUS1_OUT(0)            => open_txbufstatus_lane3,
                     
          RXCHANISALIGNED0_OUT           => CHBONDDONE_OUT_3,
          RXCHANISALIGNED1_OUT           => CHBONDDONE_OUT_4,
          RXCHANREALIGN0_OUT             => open,
          RXCHANREALIGN1_OUT             => open,

         ----------------- Receive Ports - RX Polarity Control Ports ----------------
          RXPOLARITY0_IN                => RXPOLARITY_IN_3,
          RXPOLARITY1_IN                => RXPOLARITY_IN_4,
        --------------------- Shared Ports - Tile and PLL Ports --------------------
          CLKIN_IN                      => REFCLK,

          GTXRESET_IN                   => GTXRESET_IN,
          PLLLKDET_OUT                   => plllkdet_lane1_i,
          REFCLKOUT_OUT_1                  => REFCLKOUT_OUT_2,
          RESETDONE0_OUT                 => resetdone0_lane1_i,
          RESETDONE1_OUT                 => resetdone1_lane1_i,
          
          ---------------- Transmit Ports - 8b10b Encoder Control Ports --------------
          TXCHARISK0_IN     => TXCHARISK_IN_3,
          TXCHARISK1_IN     => TXCHARISK_IN_4,
          ------------------ Transmit Ports - TX Data Path interface -----------------
          TXDATA0_IN                 => TXDATA_IN_3,
          TXDATA1_IN                 => TXDATA_IN_4,
          TXOUTCLK0_OUT                  => TXOUTCLK1_OUT_3,
          TXOUTCLK1_OUT                  => TXOUTCLK1_OUT_4,
          TXRESET0_IN                   => TXRESET_IN_3 ,
          TXRESET1_IN                   => TXRESET_IN_4,
          TXUSRCLK0_IN                  => TXUSRCLK_IN,
          TXUSRCLK1_IN                  => TXUSRCLK_IN,
          TXUSRCLK20_IN                 => TXUSRCLK2_IN,
          TXUSRCLK21_IN                 => TXUSRCLK2_IN,
          --------------- Transmit Ports - TX Driver and OOB signalling --------------
          TXN0_OUT                       => TX1N_OUT_3,
          TXN1_OUT                       => TX1N_OUT_4,
          TXP0_OUT                       => TX1P_OUT_3,
          TXP1_OUT                       => TX1P_OUT_4
);           

end BEHAVIORAL;    
 

 Hello thanks for your time. Here are my hierarchy picture and my wrapper.vhd. But as per your question I didnot inserted anything in my wrapper file and I am not aware of this too. Please tell me exactly what to do. 

Regards,

jeevanreddymandali
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Xilinx Employee
Xilinx Employee
10,818 Views
Registered: ‎09-20-2012

Re: Cannot add fifo.ngc file to my top module

Jump to solution

Hi,

 

As you are using VHDL, there is no need of seperate wrapper file. 

 

In top level write a component declaration statement for the FIFO core and instantiate it. For instantiation template, you can use .vho file generated at IP core directory.

 

If you have already instantiated the FIFO properly then remove the fifo_generator_v7_2.xco file from project hierarchy and re-add the .ngc file and see if it is shown in hierarchy.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Registered: ‎11-03-2013

Re: Cannot add fifo.ngc file to my top module

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Hello Deepika, I already did that, I added a component and instantiated it. But I am unable to add .ngc file. You can see from my snap that the fifo.vhd file is in place under the top module, but fifo.ngc is under unassigned user library modules. Please help me with that.
jeevanreddymandali
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Xilinx Employee
Xilinx Employee
10,810 Views
Registered: ‎09-20-2012

Re: Cannot add fifo.ngc file to my top module

Jump to solution

If you have already instantiated the FIFO properly then remove the fifo_generator_v7_2.xco file from project hierarchy and re-add the  fifo_generator_v7_2.ngc file and see if it is shown in hierarchy.

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
16,228 Views
Registered: ‎07-11-2011

Re: Cannot add fifo.ngc file to my top module

Jump to solution

Hi,

 

What is the purpose that you have brought FIFO_gen_7.2.ngc  in this project instead of genearting the core and instantiating the .vho?

What is your ISE version ? do you wanted to use old FIFO core and hence preferred this approcah?

If 7.2 FIFO is generated with your existing ISE and if you know where to interface the FIFO in your project (write and read clocks, enables) add .xco and use .vho file to declare the component and insantiate the FIFO.

 

Hope this helps

 

Regards,

Vanitha.

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Registered: ‎11-03-2013

Re: Cannot add fifo.ngc file to my top module

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Guys, Deepika,Vanitha, thanks for your time. But I do not know what happened, the .ngc file actually got added to the project by itself when I tried to add it the next day and my project is running smooth now.
Regards,
jeevanreddymandali
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