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Contributor
Contributor
1,254 Views
Registered: ‎12-24-2017

Cannot create design entry

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 I tried to add a third gpio block and got [BD 41-1075] Cannot create address segment for </axi_gpio_2/S_AXI/Reg> in </S_AXI_0> at 0x00000000 [ 64K ]. The proposed address exceeds the base address limitations <0x00000000 [ 4K ]> of the interface(s) </S_AXI_0> through which this peripheral is accessed by this address space

 

https://image.prntscr.com/image/Afbz_RMyQ8u2jNHXrLIBSQ.png

 

I can't add them manually in adress editor .Should I deleted the Gpio block that has 2 outputs?

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Scholar
Scholar
1,600 Views
Registered: ‎03-28-2016

Re: Cannot create design entry

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Let IPI assign the peripheral addressing.  In the Address Editor, select the "Auto Assign Address" button.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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Observer
Observer
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Registered: ‎12-06-2016

Re: Cannot create design entry

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Hi,

 

Strange that base address for the slave AXI indicated in error message is 0x00000000!!. Because normally GP0 slave axi range starts from 0x40000000 +1G and GP1 from 0x80000000 +1G. Anything out of thess ranges will not fall under PL Slave interface area.

 

 

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Scholar
Scholar
1,601 Views
Registered: ‎03-28-2016

Re: Cannot create design entry

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Let IPI assign the peripheral addressing.  In the Address Editor, select the "Auto Assign Address" button.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

View solution in original post

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Contributor
Contributor
1,206 Views
Registered: ‎12-24-2017

Re: Cannot create design entry

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It worked but should I set some auto-updater in Vivado?I used that function few times and got error.Closed Vivado and now worked.

Wasted 2 hours for nothing...

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Contributor
Contributor
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Registered: ‎12-24-2017

Re: Cannot create design entry

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Now I get

[Place 30-415] IO Placement failed due to overutilization. This design contains 105 I/O ports
while the target device: 7z010 package: clg400, contains only 67 available user I/O. The target device has 230 usable I/O pins of which 163 are already occupied by user-locked I/Os.
To rectify this issue:
1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary.
2. Check the top-level ports of the design to ensure the correct number of ports are specified.
3. Consider design changes to reduce the number of I/Os necessary.

[Place 30-68] Instance GPIO_tri_o_OBUF[2]_inst (OBUF) is not placed

 

I tried to set the pins to Connector JB bottom line like this.

 

#set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { jb_n[1] }]; #IO_L8N_T1_34 Sch=JB1_N
#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { jb_p[1] }]; #IO_L8P_T1_34 Sch=JB1_P
#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { jb_n[2] }]; #IO_L1N_T0_34 Sch=JB2_N
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { jb_p[2] }]; #IO_L1P_T0_34 Sch=JB2_P
#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { jb_n[3] }]; #IO_L18N_T2_34 Sch=JB3_N
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { jb_p[3] }]; #IO_L18P_T2_34 Sch=JB3_P
#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { jb_n[4] }]; #IO_L4N_T0_34 Sch=JB4_N
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jb_p[4] }]; #IO_L4P_T0_34 Sch=JB4_P
set_property PACKAGE_PIN W14 [get_ports {GPIO_tri_o[3]}]
set_property PACKAGE_PIN T11 [get_ports {GPIO_tri_o_tri_o[2]}]
set_property PACKAGE_PIN V16 [get_ports {GPIO_tri_o[0]}]
set_property PACKAGE_PIN V12 [get_ports {GPIO_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_tri_o[0]}]

 

Did I missed something?

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Scholar
Scholar
1,163 Views
Registered: ‎03-28-2016

Re: Cannot create design entry

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Your pin constraints look ok.  The software is complaining that your design has 105 IO while there are only 67 pins available to use.  Check your design to see what other IO you have.  Reduce that number below 67.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com